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preliminary information AMD-751 system controller data sheet publication # 21910 rev: d issue date: august 1999 tm
preliminary information ? 1999 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of amd?s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice. trademarks amd, the amd logo, amd athlon, and combinations thereof, amd-750, AMD-751, and amd-756 are trade- marks, and amd-k6 is a registered trademark of advanced micro devices, inc. alpha is a trademark of digital equipment corporation. microsoft is a registered trademark of microsoft corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
table of contents iii 21910d?august 1999 AMD-751? system controller data sheet preliminary information contents revision history xiii conventions, abbreviations, and references xix signals and bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix data terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix abbreviations and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . xx related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi 1 features 1 1.1 amd athlon? system bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 integrated memory controller . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 pci bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 agp features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2overview 7 2.1 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 pci controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 accelerated graphics port (agp) . . . . . . . . . . . . . . . . . 10 2.1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.6 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.7 power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 interface levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 ordering information 15
iv table of contents AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4 signal descriptions 17 4.1 processor interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 clkfwdrst (clock forward reset) . . . . . . . . . . . . . 17 4.1.2 connect (connect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 procrdy (processor ready) . . . . . . . . . . . . . . . . . . . . 17 4.1.4 saddin[14:2]# (address/command) . . . . . . . . . . . . . . 18 4.1.5 saddinclk# (system address in clock) . . . . . . . . . . 18 4.1.6 saddout[14:2]# (system address out) . . . . . . . . . . . 18 4.1.7 saddoutclk# (system address out clock) . . . . . . 19 4.1.8 scheck[7:0]# (data bus check byte) . . . . . . . . . . . . . 19 4.1.9 sdata[63:0]# (processor data channel) . . . . . . . . . . 20 4.1.10 sdatainclk[3:0]# (system data in clock) . . . . . . . 20 4.1.11 sdatainval# (system data in valid) . . . . . . . . . . . 21 4.1.12 sdataoutclk[3:0]# (system address out clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.13 sysclk (system clock) . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.1 ad[31:0] (pci address/data bus) . . . . . . . . . . . . . . . . . 22 4.2.2 c/be[3:0]# (pci command/byte enables) . . . . . . . . . . 23 4.2.3 devsel# (pci device select) . . . . . . . . . . . . . . . . . . . 23 4.2.4 frame# (pci cycle frame) . . . . . . . . . . . . . . . . . . . . . 24 4.2.5 gnt[4:0]# (pci bus grant) . . . . . . . . . . . . . . . . . . . . . . 24 4.2.6 irdy# (initiator ready) . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.7 lock# (pci bus lock) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.8 par (pci bus parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.9 pclk (pci clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.10 pgnt# (pci grant to peripheral bus controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2.11 preq# (pci request from peripheral bus controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.12 req[4:0]# (pci bus request) . . . . . . . . . . . . . . . . . . . . 27 4.2.13 reset# (reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2.14 serr# (system error) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.15 stop# (pci bus stop) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.16 trdy# (target ready) . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.17 wsc# (write snoop complete) . . . . . . . . . . . . . . . . . . . 29
table of contents v 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.3 dram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.1 cs[5:0]# (chip selects) . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.2 dqm[7:0]# (data mask) . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.3 mada[14:0] and madb[14:0] (memory address) . . . . 30 4.3.4 mcke[2:0] (sdram clock enable) . . . . . . . . . . . . . . . 31 4.3.5 mdat[63:0] (memory data) . . . . . . . . . . . . . . . . . . . . . 31 4.3.6 meccd[7:0] (memory ecc) . . . . . . . . . . . . . . . . . . . . . 32 4.3.7 scas[2:0]# (sdram column address strobes) . . . . . 32 4.3.8 sdram clk_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.9 sdram clk_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3.10 sras[2:0]# (sdram row address strobes) . . . . . . . . 33 4.3.11 we[2:0]# (sdram memory write enables) . . . . . . . . 33 4.4 agp/pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4.1 a_ad[31:0] (address/data bus) . . . . . . . . . . . . . . . . . . 34 4.4.2 a_c/be[3:0]# (pci command/byte enables) . . . . . . . . 35 4.4.3 a_clk (agp clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.4 a_devsel# (pci device select) . . . . . . . . . . . . . . . . . 36 4.4.5 a_frame# (pci cycle frame) . . . . . . . . . . . . . . . . . . 36 4.4.6 a_gnt# (agp bus grant) . . . . . . . . . . . . . . . . . . . . . . . 36 4.4.7 a_irdy# (initiator ready) . . . . . . . . . . . . . . . . . . . . . . 37 4.4.8 a_par (pci bus parity) . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.9 a_req# (agp bus request) . . . . . . . . . . . . . . . . . . . . . 38 4.4.10 a_serr# (system error) . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.11 a_stop# (agp bus stop) . . . . . . . . . . . . . . . . . . . . . . . 38 4.4.12 a_trdy# (target ready) . . . . . . . . . . . . . . . . . . . . . . . 38 4.5 agp-only signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.1 adstb[1:0] (ad bus strobe) . . . . . . . . . . . . . . . . . . . 40 4.5.2 pipe# (apg pipeline) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5.3 rbf# (read buffer full) . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5.4 sba[7:0] (sideband address bus) . . . . . . . . . . . . . . . . . 41 4.5.5 sbstb (sideband strobe) . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.6 st[2:0] (status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6 miscellaneous signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.1 rom_sck (srom clock) . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.2 rom_sda (srom data) . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.3 scan_en# (scan enable) . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.4 tristate# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
vi table of contents AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5 functional operation 45 5.1 system addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2 processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.1 bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.2 biu start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2.3 processor write posting . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2.4 read buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.1 memory request organizer (mro) . . . . . . . . . . . . . . . 59 5.3.2 memory controller (mct) . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.3 address mapping and memory organization . . . . . . . 65 5.3.4 sdram interface memory . . . . . . . . . . . . . . . . . . . . . . 67 5.3.5 shadow ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.6 synchronous dram (sdram) . . . . . . . . . . . . . . . . . . . 72 5.4 pci bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.1 memory coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.2 pci arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.3 pci configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.4 pci southbridge signals . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.5 pci parity/ecc errors . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.6 pci-to-memory/pci-from-memory and other pci targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.7 pci-to-processor bus read transactions . . . . . . . . . . . 81 5.4.8 processor-to-pci bus write transactions . . . . . . . . . . . 81 5.4.9 pci accesses by an initiator . . . . . . . . . . . . . . . . . . . . . 82 5.5 accelerated graphics port (agp) . . . . . . . . . . . . . . . . . . . . . 83 5.5.1 agp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.5.2 the agp queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.5.3 agp system dram interface (sdi) . . . . . . . . . . . . . . . 90 5.5.4 agp arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.5.5 agp data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5.5.6 pci transactions on the agp bus . . . . . . . . . . . . . . . . . 93 5.5.7 graphics adapters and main memory . . . . . . . . . . . . . 94 5.5.8 agp virtual address space (aperture) range and size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.5.9 gart cache operation . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.7 phase locked loop (pll) features . . . . . . . . . . . . . . . . . . . 110
table of contents vii 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 6 typical settings 111 7 configuration registers 123 7.1 pci configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . 123 7.2 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.3 function 0, device 0 registers (processor-to-pci bridge, memory controller, etc.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.4 device 1 registers (agp and pci-to-pci bridge) . . . . . . . 161 7.5 memory-mapped control registers . . . . . . . . . . . . . . . . . . . 173 8 electrical data 179 8.1 absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 8.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 8.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 8.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 8.4.1 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . 183 9 switching characteristics 185 9.1 sysclk switching characteristics . . . . . . . . . . . . . . . . . . . 186 9.2 valid delay, float, setup, and hold timings . . . . . . . . . . . 188 9.3 pci interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.4 sdram interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . 190 9.5 agp interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.6 amd athlon ? system bus timings . . . . . . . . . . . . . . . . . . . 193 10 i/o buffer characteristics 195 10.1 i/o buffer model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2 i/o model application note . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.3 i/o buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 196
viii table of contents AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 11 pin designations 197 12 package specifications 201 index 205
list of figures ix 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information list of figures figure 1. amd-750 ? chipset system block diagram . . . . . . . . . . . . . . . 6 figure 2. AMD-751 ? system controller block diagram. . . . . . . . . . . . 12 figure 3. amd athlon ? processor-based system clocking . . . . . . . . . 14 figure 4. ordering information elements . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. system memory view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6. address mapping for x86 legacy . . . . . . . . . . . . . . . . . . . . . . 47 figure 7. block diagram of the bus interface unit (biu) . . . . . . . . . . . 53 figure 8. sip protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 9. amd athlon ? system bus data buffers (biu) . . . . . . . . . . . 58 figure 10. memory request organizer (mro) block diagram . . . . . . . 60 figure 11. memory queue arbiter (mqa) block diagram . . . . . . . . . . . 61 figure 12. memory controller (mct) block diagram . . . . . . . . . . . . . . . 63 figure 13. sdram interface example . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 14. dram refresh timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 15. refresh timer and counters . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 16. AMD-751 ? system controller clocking scheme. . . . . . . . . . 75 figure 17. 100-mhz sdram detailed timing . . . . . . . . . . . . . . . . . . . . . 76 figure 18. agp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 19. agp queues and buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 20. AMD-751 ? system controller arbiters . . . . . . . . . . . . . . . . . 91 figure 21. address remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 22. cache hierarchy (conventional two-level scheme) . . . . . . 96 figure 23. conventional gart scheme ? multiple tables . . . . . . . . . . 96 figure 24. page translation structures. . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 25. page directory entry (pde) definition . . . . . . . . . . . . . . . . . 99 figure 26. address translation flow chart . . . . . . . . . . . . . . . . . . . . . . 101 figure 27. two-level gart translation scheme . . . . . . . . . . . . . . . . . 103 figure 28. another view of the two-level indexing scheme . . . . . . . 104 figure 29. power management signal connections. . . . . . . . . . . . . . . . 106 figure 30. acpi power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 31. sysclk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 32. clk waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
x list of figures AMD-751? system controller data sheet 21910d ? august 1999 preliminary information figure 33. setup, hold, and valid delay timings . . . . . . . . . . . . . . . . . 188 figure 34. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 35. bottom side view of package . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 36. top and side views of package . . . . . . . . . . . . . . . . . . . . . . . 202
list of tables xi 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information list of tables table 1. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx table 2. acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii table 3. sdram organizations supported . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. gart table-cache sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. AMD-751 ? system controller interface voltages . . . . . . . . . . 13 table 6. valid combinations for ordering parts . . . . . . . . . . . . . . . . . . . 15 table 7. AMD-751 ? system controller memory address map . . . . . . . 46 table 8. amd athlon ? processor special cycle encoding . . . . . . . . . . 48 table 9. sip protocol states and actions . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 10. sdram memory organizations . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 11. pc-100 rev. 1.0 sdram dimm part nomenclature. . . . . . . . 72 table 12. sdram dimm loading analysis . . . . . . . . . . . . . . . . . . . . . . . . 74 table 13. key sdram dimm timing variables . . . . . . . . . . . . . . . . . . . . 77 table 14. summary of gart terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 15. mask bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 16. AMD-751 ? system controller msr settings . . . . . . . . . . . . . 111 table 17. configuration port register summary . . . . . . . . . . . . . . . . . . 125 table 18. function 0, device 0 configuration registers . . . . . . . . . . . . 126 table 19. function 0, device 1 configuration registers . . . . . . . . . . . . 128 table 20. memory space configuration registers (bar1 + n) . . . . . . . 129 table 21. power management configuration registers (bar2 + n) . . 129 table 22. size field versus agp memory allocation . . . . . . . . . . . . . . . 135 table 23. mapping processor address lines to memory address lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 24. absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 25. operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 26. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 27. amd athlon ? system bus/AMD-751 ? system controller dc specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 28. typical and maximum power dissipation . . . . . . . . . . . . . . . . 183 table 29. heatsinks for the AMD-751 ? system controller . . . . . . . . . . 183 table 30. thermal interface material for the AMD-751 ? system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
xii list of tables AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 31. sysclk switching characteristics for 100-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 32. a_clk switching characteristics for 66-mhz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 33. pclk switching characteristics for 33-mhz pci bus . . . . . . 187 table 34. pci interface timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 35. dram interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 36. agp 1x mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 37. agp 2x mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 38. amd athlon ? system bus/AMD-751 ? system controller ac specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 39. symbol notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 40. 492-pin pbga 35.0 mm by 35.0 mm package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 41. geometric tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
revision history xiii 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information revision history date rev description august 1999 d initial public release
xiv revision history AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information
conventions, abbreviations, and references xv 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information conventions, abbreviations, and references this section contains information about the conventions and abbreviations used in this document and a list of related publications. signals and bits n active-low signals ? signal names containing a pound sign, such as sfill#, indicate active-low signals. they are asserted in their low-voltage state and negated in their high-voltage state. when used in this context, high and low are written with an initial upper case letter. n signal ranges ? in a range of signals, the highest and lowest signal numbers are contained in brackets and separated by a colon (for example, d[63:0]). n reserved bits and signals ? signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. these bits and signals are reserved by amd for future implementations. when software reads registers with reserved bits, the reserved bits must be masked. when software writes such registers, it must first read the register and change only the non-reserved bits before writing back to the register. n three-state ? in timing diagrams, signal ranges that are high impedance are shown as a straight horizontal line half-way between the high and low levels. n invalid and don ? t-care ? in timing diagrams, signal ranges that are invalid or don't-care are filled with a screen pattern. data terminology the following list defines data terminology: n quantities ? a word is two bytes (16 bits) a doubleword is four bytes (32 bits) a quadword is eight bytes (64 bits) an amd athlon ? processor cache line is eight quadwords (64 bytes)
xvi conventions, abbreviations, and references AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information n addressing ? memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. n abbreviations ? the following notation is used for bits and bytes: kilo (k, as in 4-kbyte page) mega (m, as in 4 mbits/sec) giga (g, as in 4 gbytes of memory space) see table 2 for more abbreviations. n little-endian convention ? the byte with the address xx...xx00 is in the least-significant byte position (little end). in byte diagrams, bit positions are numbered from right to left ? the little end is on the right and the big end is on the left. data structure diagrams in memory show low addresses at the bottom and high addresses at the top. when data items are aligned, bit notation on a 64-bit data bus maps directly to bit notation in 64-bit-wide memory. because byte addresses increase from right to left, strings appear in reverse order when illustrated. n bit ranges ? in text, bit ranges are shown with a dash (for example, bits 9 ? 1). when accompanied by a signal or bus name, the highest and lowest bit numbers are contained in brackets and separated by a colon (for example, ad[31:0]). n bit values ? bits can either be set to 1 or cleared to 0. n hexadecimal and binary numbers ? unless the context makes interpretation clear, hexadecimal numbers are followed by an h and binary numbers are followed by a b. abbreviations and acronyms table 2 contains the definitions of abbreviations used in this document. table 1. abbreviations abbreviation meaning aampere f farad g giga- gbit gigabit gbyte gigabyte
conventions, abbreviations, and references xvii 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information hhenry h hexadecimal k kilo- kbyte kilobyte m mega- mbit megabit mbyte megabyte mhz megahertz m milli- ms millisecond mw milliwatt micro- a microampere f microfarad h microhenry s microsecond v microvolt n nano- na nanoampere nf nanofarad nh nanohenry ns nanosecond ohm ohm ppico- pa picoampere pf picofarad ph picohenry ps picosecond s second vvolt wwatt table 1. abbreviations (continued) abbreviation meaning
xviii conventions, abbreviations, and references AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 2 contains the definitions of acronyms used in this document. table 2. acronyms abbreviation meaning aat agp address translator ack acknowledge acpi advanced configuration and power interface agp accelerated graphics port apci agp peripheral component interconnect api application programming interface apic advanced programmable interrupt controller ate address translation engine awq pci/apci write queue axq agp transaction queue bar base address register bios basic input/output system bist built-in self-test biu bus interface unit cs chip select csq system data and control queue cq command queue ddr double-data rate dimm dual inline memory module dma direct memory access dram direct random access memory ecc error correcting code eide enhanced integrated device electronics eisa extended industry standard architecture eprom enhanced programmable read only memory ev6 digital ? alpha ? bus fid frequency integer divisor fifo first in, first out gart graphics address remapping table gdc gart directory cache gfe gart front end gtc gart table cache
conventions, abbreviations, and references xix 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information gtw gart table walk hstl high-speed transistor logic iack interrupt acknowledge ide integrated device electronics imb interrupt message bus isa industry standard architecture jedec joint electron device engineering council jtag joint test action group lan large area network lru least-recently used lsb least significant bit lvttl low voltage transistor transistor logic ma memory address mct memory controller md memory data mda monochrome display adapter mdp memory data path mqa memory queue arbiter mra memory request arbiter mrf memory read fifo mrl memory read line mrm memory read multiple mro memory request organizer mrq memory read queue mrs memory request scheduler msb most significant bit mtrr memory type and range registers mwf memory write fifo mwi memory write-and-invalidate mwq memory write queue mws memory write selector mux multiplexer nmi non-maskable interrupt od open drain table 2. acronyms (continued) abbreviation meaning
xx conventions, abbreviations, and references AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information pbga plastic ball grid array pa physical address pci peripheral component interconnect pde page directory entry pdt page directory table ph page hit pll phase locked loop pmsm power management state machine pos power-on suspend post power-on self-test ppa physical page address ppq pending probes queue pq probe queue pra probe response alert agent psq probe system data and control queue pt page tables pte page table entries ram random access memory rbn round robin rdq read request queue rom read only memory rxa read acknowledge queue sba sideband address sdi system dram interface sdram synchronous direct random access memory sip serial initialization packet smbus system management bus smc sdram memory controller spd serial presence detect sram synchronous random access memory srom serial read only memory srq sysdc read queue sysdc system data commands tlb translation lookaside buffer tom top of memory ttl transistor transistor logic table 2. acronyms (continued) abbreviation meaning
conventions, abbreviations, and references xxi 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information vas virtual address space vpa virtual page address vga video graphics adapter whami who am i wbt write buffer tag wp write protect wrq write request queue usb universal serial bus xca transaction combiner agent zdb zero delay buffer table 2. acronyms (continued) abbreviation meaning
xxii conventions, abbreviations, and references AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information related publications the following books discuss various aspects of computer architecture that may enhance your understanding of amd products: amd publications amd athlon? processor data sheet , order# 21016 amd-756? peripheral bus controller data sheet , order# 22548 bus architecture pci local bus specification, revision 2.2 , pci special interest group, hillsboro, oregon, 1998. at bus design , edward solari, ieee p996 compatible, annabooks, san diego, ca, 1990. accelerated graphics port interface specification revision 2.0 , intel corporation, agp forum, 1998. x86 architecture programming the 80386 , john crawford and patrick gelsinger, sybex, san francisco, 1987. 80x86 architecture & programming , rakesh agarwal, volumes i and ii, prentice-hall, englewood cliffs, nj, 1991. general references computer architecture , john l. hennessy and david a. patterson, morgan kaufman publishers, san mateo, ca, 1990. websites visit the amd website for documentation of amd products. www.amd.com other websites of interest include the following: n jedec home page ? www.jedec.org n ieee home page ? www.computer.org n agp forum ? www.agpforum.org
chapter 1 features 1 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 1 features the amd athlon? processor powers the next generation in computing platforms, delivering the ultimate performance for cutting-edge applications and an unprecedented computing experience. the amd-750 ? chipset is a highly integrated system logic solution that delivers enhanced performance for the amd athlon processor and other amd athlon system bus-compatible processors. the amd-750 chipset consists of the AMD-751 ? system controller in a 492-pin plastic ball-grid array (pbga) package and the amd-756 ? peripheral bus controller. the AMD-751 system controller features the amd athlon system bus, system memory controller, accelerated graphics port (agp) controller, and peripheral component interconnect (pci) bus controller. figure 1 on page 6 shows a block diagram for the amd-750 chipset. the AMD-751 system controller is designed with the following features: n the amd athlon system bus supports three 200-mhz high-speed channels n the 33-mhz 32-bit pci 2.2-compliant bus interface supports up to six masters n the 66-mhz agp 2.0-compliant interface supports 2x data transfer mode n high-speed memory ? the AMD-751 system controller is designed to support a 100-mhz pc-100 rev. 1.0 sdram dimms this document describes the features and operation of the AMD-751 system controller. for a description of the amd-756 peripheral bus controller, see the amd-756 ? peripheral bus controller data sheet , order# 21645. key features of the AMD-751 system controller are provided in this section.
2 features chapter 1 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 1.1 amd athlon ? system bus the amd athlon system bus has the following features: n high-performance point-to-point system bus topology n source-synchronous clocking for high-speed transfers n hstl-like low-voltage swing transceiver logic signal levels n three 200-mhz independent high-speed channels: 13-pin processor request channel 13-pin system probe channel 72-pint data transfer channel (8-bit ecc) n 1.6 gigabyte per second peak data transfer rates at 200 mhz n large 64-byte (cache line) data burst transfers n data buffers: memory write fifo (mwf) memory read fifo (mrf) pci/apci (agp-pci) write buffer pci/apci read buffer n transaction queues: command queue (cq) memory write queue (mwq) memory read queue (mrq) probe (snoop) queue (pq) 1.2 integrated memory controller the integrated memory controller has the following features: n memory request organizer (mro) ? serves as a data crossbar, determines request dependencies, and optimizes scheduling of memory requests n the AMD-751 system controller supports the following concurrences: processor-to-main-memory with pci-to-main-memory processor-to-main-memory with agp-to-main-memory processor-to-pci with pci-to-main-memory or agp-to-main-memory
chapter 1 features 3 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information n memory error correcting code (ecc) support n supports the following dram: up to three non-buffered pc-100 rev. 1.0 sdram dimms using 16-mbit, 64-mbit, and 128-mbit technology (see table 3 on page 9) 64-bit data width, plus 8-bit ecc paths flexible row and column addressing n supports up to 768 mbytes of memory n four open pages within one cs (device selected by chip select) for one quadword n default two-page leapfrog policy for eight quadword requests n bios-configurable memory-timing parameters and configuration parameters n 3.3-v memory interface operation with no external buffers n four cache lines of processor-to-dram posted write buffers with full read-around capability n concurrent dram writeback and read-around-write n burst read and write transactions n decoupled and burst dram refresh with staggered cs timing n provides the following refresh options: programmable refresh rate cas-before-ras populated banks only chipset powerdown via sdram automatic refresh command automatic refresh of idle slots ? improves bus availability for memory access by the processor or system
4 features chapter 1 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 1.3 pci bus controller the pci bus controller has the following features: n compliance with pci local bus specification, revision 2.2 n supports six pci masters n 32-bit interface, compatible with 3.3-v and 5-v pci i/o n synchronous pci bus operation up to 33 mhz n pci-initiator peer concurrence n automatic processor-to-pci burst cycle detection n four-entry, 64-bit pci master (processor or agp) write fifo n extensive utilization of fifos n zero wait-state pci initiator and target burst transfers n pci-to-dram data streaming up to 132 mbytes per second n enhanced pci command optimization, such as memory read line (mrl), memory read multiple (mrm), and memory-write-and-invalidate (mwi) n timer-enforced fair arbitration between pci initiators n supports advanced concurrency n supports retry disconnect for improved bus utilization n pci read buffer keeps track of each master n pci target request queue 1.4 agp features the agp features include the following: n bus features compliance with agp 2.0 specification synchronous 66-mhz 1x and 2x data-transfer modes multiplexed and demultiplexed transfers up to four pipelined grants support of sideband address (sba) bus n request queue features separate read-request and write-request queues reordering of high-priority requests over low-priority requests in queue
chapter 1 features 5 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information simultaneous issuing of requests from both the write queue and read queue selects next request to optimize bus utilization n transaction queues memory-to-agp and processor-to-agp transaction queues n fifo features 16-entry (64-bit) agp-to-memory write fifo 64-entry (64-bit) memory-to-agp read fifo n secondary pci bus features pipelined burst reads and writes extensive utilization of fifos n gart (graphics address remapping table) features conventional (two-level) gart scheme eight-entry, fully-associative gart table cache (gtc) three fully-associative gart directory caches (gdc) one 4-entry for pci one 8-entry for the processor one 16-entry for agp 1.5 power management the power management features include the following: n compliance support for both acpi and microsoft ? pc 98 power management n the AMD-751 system controller supports the following power states: processor halt/stop grant/sleep states power-on suspend
6 features chapter 1 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 1. amd-750? chipset system block diagram ethernet southbridge pci bus isa usb system management, lan 1394a 32-bit 16-bit eide peripheral bus controller dram 64-bit data 64-bit data + 8-bit ecc system bus memory bus serr# preq# pgnt# system controller processor system controller dram graphics agp bus 32-bit +8-bit ecc reset, initialize, interrupts bios amd-756 ? AMD-751 ? amd athlon ? wsc# sdram 13-bit saddin + 13-bit saddout
chapter 2 overview 7 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 2 overview the AMD-751 system controller is designed to optimize the interaction between the processor, dram, agp, and the pci bus with pipelined burst and concurrent transactions. each bus interface includes multiple specialized fifo buffers to enable optimum system concurrency. in the AMD-751, amd has introduced a memory-request organizer to optimize the bandwidth of the dram. the AMD-751 system controller implements the agp to provide streamlined 3d renderings and reduce graphics memory requirements. the AMD-751 is packaged in a 492-pin pbga. 2.1 system the AMD-751 system controller is capable of performing i/o transactions, single-access memory transactions, and block-access memory transactions. the amd athlon system bus is a split-transaction bus. a split-transaction bus optimizes system throughput by allowing the AMD-751 system controller to schedule tasks and thereby free the bus during resource delays. the system controller responds only to i/o cycles within its configuration-register space and to memory requests as defined in its configuration registers. all timing on the system bus is derived from the system clock (sysclk). 2.1.1 processor interface the amd athlon system bus consists of three independent high-speed channels, including a 72-bit, 200-mhz, point-to-point, non-multiplexed, source-synchronous clocked data transfer channel capable of supporting the amd athlon processor with transfer rates of 1.6 gigabyte per second. to achieve higher speed data transfers, the amd athlon system bus uses an open-drain, hstl-like signaling level. source-synchronous clocking compensates for pc board propagation delays to enable higher speed transfers.
8 overview chapter 2 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information the AMD-751 processor interface responds to processor commands, issues probes, and controls all data movement into and out of the processor. more details on the processor interface can be found in chapter 5, ? functional operation ? starting on page 45. 2.1.2 memory controller the AMD-751 system controller incorporates a high-performance dram controller with a memory-request organizer that provides the dram interface for an amd athlon processor and can support pc-100 rev. 1.0 sdram dimms at 100 mhz. the memory-request organizer serves as a data crossbar and determines request dependencies to provide optimum scheduling of memory requests. large on-chip fifos are used to decouple requests and provide concurrency. these features combine with the split-transaction processor bus to facilitate optimum use of the bus and memory bandwidths. the memory controller can address up to three slots of sdram at 100 mhz in various combinations, up to a total of 768 mbytes. the AMD-751 system controller supports the following concurrencies: n processor-to-main-memory with pci-to-main-memory n processor-to-main-memory with agp-to-main-memory n processor-to-pci-memory with pci-to-main-memory or agp-to-main-memory pc-100 rev. 1.0 sdrams dimms allow fast bursting of data between the dram and the internal controller data buffers at 100 mhz. the dram controller supports a 72-bit data path to memory and can be configured to support error correcting code (ecc), which can correct single-bit errors and detect double-bit errors for data integrity. the bios must determine the type of memory installed and program the configuration registers accordingly. the AMD-751 supports the sdram types shown in table 3 on page 9. it does not support x32 dram configurations in the 16-mbit technology. the AMD-751 logically supports the x4 configuration, but it is not recommended with unbuffered dimms.
chapter 2 overview 9 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information for more details on the memory controller, see chapter 5, ? functional operation ? starting on page 45. 2.1.3 pci controller the AMD-751 system controller is compatible with the pci local bus specification, revision 2.2 . it can operate at either 3.3 v or 5 v, and offers 64-bit to 32-bit data conversion. the AMD-751 supports up to six external pci masters. the AMD-751 implements a very high degree of internal concurrency. however, all pci-to-memory transactions are, by definition, coherent and therefore must be snooped in all processors. five separate pci fifos containing over 300 bytes of storage are utilized to facilitate concurrency. in addition, the AMD-751 prefetches eight quadwords (one amd athlon processor cache line) when performing memory reads for a pci master. enhanced pci bus commands, such as memory read line (mrl), memory read multiple (mrm), and memory table 3. sdram organizations supported sdram organization banks addressing 16m x 4 2 10 x 11 16m x 8 2 9 x 11 16m x 16 2 8 x 11 16m x 32 not supported 64m x 4 4 10 x 12 64m x 4 2 10 x 13 64m x 8 4 9 x 12 64m x 8 2 9 x 13 64m x 16 4 8 x 12 64m x 16 2 8 x 13 64m x 32 4 7 x 12 64m x 32 2 7 x 13 128m x 4 4 11 x 12 128m x 8 4 10 x 12 128m x 16 4 9 x 12 128m x 32 4 8 x 12
10 overview chapter 2 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information write-and-invalidate (mwi), maximize data throughput. the AMD-751 system controller employs a variety of techniques to minimize pci initiator read latency and dram utilization. the combination of these features allows a pci initiator to achieve the full 133-mbyte burst transfer rate. in addition, the AMD-751 contains a pci arbiter. see chapter 5, ? functional operation ? starting on page 45 for more information. 2.1.4 accelerated graphics port (agp) the accelerated graphics port (agp) is an alternate interface bus for a computer system. the agp provides a point-to-point link between a graphics controller and the memory controller. this additional pathway to memory removes 3d graphics traffic from the pci bus and provides a special access path to main memory, allowing it to function as part of graphics memory and reducing the amount of memory required on the graphics adapter. typically, the section of main memory allocated for the agp adapter would then be used to hold ? textures ? , improving the realism of 3d images. the agp bus is essentially an expansion of the standard pci local bus containing additional sideband signals and commands. the three primary enhancements to pci include pipelined memory requests, separate address and data buses, and double-pumped (2x) ac timing mode, in which data is transferred on both edges of the agp clock. double-pumping enables effective transfer rates as high as 133 mhz, generating an effective data transfer rate of up to 533 mbytes/second. the agp bus supports pci as well as agp transfers. as usual, the a_frame# signal indicates pci transfers, while a new signal, pipe#, is used to signify agp transfers. to avoid confusion in this document, the system-wide pci bus is referred to as the primary pci bus, and the pci implementation on the agp bus is referred to as the secondary pci bus or a-pci. the AMD-751 implements an agp 1.0-compliant interface, which provides a 32-bit-wide data path operating at either 66 mhz or 133 mhz. the AMD-751 can queue 16 outstanding agp transactions. see chapter 5, ? functional operation ? starting on page 45 for more information.
chapter 2 overview 11 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information the AMD-751 system controller functions as a pci target on the agp bus. when the agp bus functions in agp mode, the graphics controller is the agp initiator and the AMD-751, which contains the memory controller, functions as the agp target. the AMD-751 implements a full-featured graphics-address remapping table (gart). as shown in table 4, this gart implementation is distributed with individual table caches at each interface and a common directory cache in the table-walk logic that contains four fully associative entries. see chapter 5, ? functional operation ? starting on page 45 for more details on the gart. table 4. gart table-cache sizes interface gart table-cache size/organization agp 16 entries, fully associative pci & a-pci 4 entries, fully associative processor 8 entries, fully associative
12 overview chapter 2 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 2.1.5 block diagram figure 2 shows the full complement of features and functions built into the AMD-751 system controller system logic. figure 2. AMD-751 ? system controller block diagram sdataoutclk[3:0]# ad[31:0] c/be[4:0]# devsel# frame# irdy# lock# par preq# gnt[4:0]# pgnt# req[4:0]# serr# stop# trdy# dqm[7:0]# mada[14:0] madb[14:0] mdat[63:0] meccd[7:0] cs[5:0]# sras[2:0]# we[2:0]# sysclk pclk reset# a_ad[31:0] a_c/be[3:0]# a_devsel# a_frame# a_irdy# a_par rbf# a_gnt# a_req# a_serr# a_stop# a_trdy# sba[7:0] st[2:0] pipe# adstb1 sbstb pci interface memory controller (mct) agp/pci interface adstb0 scas[2:0]# sdramclkout clock circuitry memory request (mro) organizer saddout[14:2]# sdata[63:0]# sdatainclk[3:0]# scheck[7:0]# saddoutclk# sdatainval# procrdy clkfwdrst connect saddinclk# processor interface (biu) saddin[14:2]# tw-fifo tr-fifo mr-fifo rm-fifo pci-apc-fifo tr-fifo tw-fifo mw-fifo mr-fifo wr fifo rd fifo agp rd-fifo agp-wr-fifo sdi wr fifo rd fifo agp/pci mem sdramclkin mcke[2:0] wsc# a_clk
chapter 2 overview 13 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 2.1.6 package the AMD-751 is packaged in a 492-ball, 35-mm plastic ball grid array (pbga). 2.1.7 power the AMD-751 operates from a 3.3-v v dd supply and dissipates 4.5 watts (w) operating under worst-case conditions. (maximum v dd is with heavy bus traffic.) the AMD-751 implements the power-on-suspend (pos) power management state. to implement the pos state, the AMD-751 provides two facilities ? sdram self-refresh and pci master grant suspend. sdrams are put in a self-refresh mode by the deassertion of the mcke[2:0] pins. the AMD-751 enters that mode in a stop grant state. careful routing of this signal on the board is important to ensure that it stays clean when it is asserted or deasserted. pci master grants are disabled via register bit 0 in bar2 offset 0h (see page 177). 2.2 interface levels a complete pinout is shown in chapter 12, ? package specifications ? on page 201. the rough grouping of signal types is shown in table 5. table 5. AMD-751 ? system controller interface voltages interface group voltages processor od open drain, pulled to 1.6 v sdram lvttl 3.3 v pci pci 3.3 v, 5 v tolerant agp agp 3.3 v
14 overview chapter 2 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 2.3 clocking the AMD-751 system controller receives a 100-mhz system clock and a 33-mhz pci clock. the AMD-751 generates and drives the 100-mhz sdram clocks through a zero-delay buffer. the 66-mhz agp clock is provided by the system clock generator as shown in figure 3. it uses a non-jtag, partial-scan scheme for silicon and motherboard testability (nand tree). figure 3. amd athlon ? processor-based system clocking clock generator (pll) pci slot 100 mhz 66 mhz 33 mhz agp slot amd-756 ? southbridge AMD-751 ? northbridge zero delay buffer (zdb) pc-100 rev. 1.0 sdram dimms
chapter 3 ordering information 15 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 3 ordering information amd standard products are available in several packages and operating ranges. the order number is formed by a combination of the elements shown in figure 4. table 6 shows valid combinations of elements. contact your amd representative for detailed ordering information. figure 4. ordering information elements AMD-751 a c family/core AMD-751 package type a = plastic ball grid array c = commercial temperature range case temperature table 6. valid combinations for ordering parts opn package type operating voltage case temperature AMD-751ac 492-pin pbga atx 3.135 v ? 3.6 v 85 c note: valid combinations are configurations that are or will be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations.
16 ordering information chapter 3 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information
chapter 4 signal descriptions 17 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4 signal descriptions 4.1 processor interface signals 4.1.1 clkfwdrst (clock forward reset) output summary clkfwdrst resets the source-synchronous clock circuitry for the processor. driven this signal is negated by reset#. it is asserted off the rising edge of sysclk. 4.1.2 connect (connect) output summary connect is an output from the AMD-751 system controller and is used for power management and source-synchronous clock initialization at reset. driven this signal is negated by reset#. it is asserted off the rising edge of sysclk. 4.1.3 procrdy (processor ready) input summary procrdy is an input to the AMD-751 system controller and is used for power management and source-synchronous clock initialization at reset. sampled this signal is sampled on the rising edge of sysclk.
18 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.1.4 saddin[14:2]# (address/command) output summary the saddin[14:2]# bus is the unidirectional system probe channel to the processor. it is used to transfer probes or data movement commands into the processor. all probes and commands on the saddin[14:2]# channel are skew-aligned with the source-synchronous clock, saddinclk#. during pci-to-dram cycles, the AMD-751 system controller drives the saddin[14:2]# bus to snoop (inquire cycle) the processor cache. driven the AMD-751 system controller drives the saddin[14:2]# channel on each edge of saddinclk#. 4.1.5 saddinclk# (system address in clock) output summary saddinclk# is the single-ended source-synchronous clock for the saddin[14:2]# bus driven by the AMD-751 system controller. each clock edge is used to transfer probes or data movement commands to the processor. driven this signal is driven inactive (negated) when the clkfwdrst signal is active (true). when clkfwdrst is deasserted, saddinclk# runs continuously. 4.1.6 saddout[14:2]# (system address out) input summary the saddout[14:2]# channel is the unidirectional system address interface from the processor to the AMD-751 system controller. the saddout[14:2]# channel is used to transfer processor requests to the system. all commands on this channel are skew-aligned with the source-synchronous clock, saddoutclk#.
chapter 4 signal descriptions 19 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information sampled the saddout[14:2]# channel is sampled by the AMD-751 system controller on each edge of saddoutclk#. the AMD-751 system controller samples commands driven by the processor on the saddout[14:2]# channel and forwards them to the pci bus, agp bus, or dram, depending on the address range and AMD-751 configuration. 4.1.7 saddoutclk# (system address out clock) input summary saddoutclk# is the single-ended source-synchronous clock for the saddout[14:2]# channel driven by the processor. each edge is used to transfer commands. this signal is driven inactive (negated) when the clkfwdrst signal is active (true). when clkfwdrst is deasserted, saddoutclk# runs continuously. 4.1.8 scheck[7:0]# (data bus check byte) bidirectional summary scheck[7:0]# contains the ecc check bits for data transferred on the sdata[63:0]# bus. driven, sampled, and floated as outputs: the AMD-751 system controller drives scheck[7:0]# with valid data. as inputs: during write cycles, the AMD-751 system controller samples scheck[7:0]#. scheck[7:0]# is floated out of reset#. it remains floated except when driven with write data by the processor, by read data (writeback data) from the cache, or by read data from the AMD-751 system controller.
20 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.1.9 sdata[63:0]# (processor data channel) bidirectional summary the sdata[63:0]# channel is the bidirectional interface to and from the processor and system for data movement. data is skew-aligned with either sdatainclk[3:0]# or sdataoutclk[3:0]#. each edge is used to transfer data. note: in/out is relative to the processor. the sdata[63:0]# channel connects to the 64-bit data channel of the processor. each of the four words of data that comprise this channel is qualified by a corresponding clock (sdatainclk[3:0]# or sdataoutclk[3:0]#). driven, sampled, and floated as outputs: the AMD-751 system controller drives the sdata[63:0]# channel with valid data on each edge of the system address clocks (sdatainclk[3:0]#). as inputs: during write cycles, the AMD-751 system controller samples the sdata[63:0]# channel on each edge of sdataoutclk[3:0]#. sdata[63:0]# is floated out of reset#. it remains floated except when driven with write data by the processor, by read data (writeback data) from the cache, or by read data from the AMD-751 system controller. 4.1.10 sdatainclk[3:0]# (system data in clock) output summary sdatainclk[3:0]# is the single-ended source-synchronous clock driven by the AMD-751 system controller to transfer data on sdata[63:0]#. each 16-bit data word is skew-aligned with this clock. each edge is used to transfer data. driven this signal is driven inactive (negated) when the clkfwdrst signal is active (true). when clkfwdrst is deasserted, sdatainclk# runs continuously.
chapter 4 signal descriptions 21 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.1.11 sdatainval# (system data in valid) output summary sdatainval# is driven by the AMD-751 system controller and controls the flow of data into the processor. sdatainval# can be used to introduce an arbitrary number of cycles between octawords (128 bits). driven this signal is negated by reset#. sdatainval# is asserted off the rising edge of saddinclk. 4.1.12 sdataoutclk[3:0]# (system address out clock) input summary sdataoutclk[3:0]# is the single-ended source-synchronous clock driven by the processor and is used to transfer data on the sdata[63:0]# channel. each 16-bit data word is skew-aligned with this clock. each edge is used to transfer data. this signal is driven inactive (negated) when the clkfwdrst signal is active (true). when clkfwdrst is deasserted, sdataoutclk# runs continuously. 4.1.13 sysclk (system clock) input summary sysclk is a single-ended input clock signal provided to the phase locked loop (pll) of the AMD-751 system controller from the system-clock generator. it is set at 100 mhz operation.
22 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.2 pci interface signals 4.2.1 ad[31:0] (pci address/data bus) bidirectional summary the ad[31:0] bus contains the standard, multiplexed pci address and data lines. ad[31:0] contains a physical address during the first clock of a pci transaction, and data during subsequent clocks. the address is driven when frame# is asserted, and data is driven or received in subsequent cycles. when the AMD-751 system controller is the pci initiator, these lines are outputs during the address and write data phases of a transaction, and inputs during the read data phases. when the AMD-751 is the pci target, these lines are inputs during the address and write data phases of a transaction, and outputs during the read data phases. driven, sampled, and floated as outputs: as an initiator, the AMD-751 system controller drives ad[31:0] with a valid address off the first rising edge of pclk after it becomes the pci bus master. during the first clock that frame# is asserted, ad[31:0] contains the address. during subsequent clocks, ad[31:0] contains data. as inputs: the AMD-751 system controller samples ad[31:0] on the rising edge of pclk. during the first clock after frame# is asserted, the AMD-751 loads the bus contents into its internal address register. on each subsequent clock in which both trdy# and irdy# are asserted, ad[31:0] loads data into its data fifo. ad[31:0] is floated for one clock in between the address phase and the data phase of a read transfer. ad[31:0] is also floated during reset# and when there is no initiator driving the bus.
chapter 4 signal descriptions 23 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.2.2 c/be[3:0]# (pci command/byte enables) bidirectional summary c/be[3:0]# contain the pci command during the first clock cycle that frame# is asserted. these signals serve as a byte-enable signal for subsequent cycles. driven, sampled, and floated as outputs: the AMD-751 system controller drives c/be[3:0]# with a valid command or byte enables off the rising edge of pclk. as inputs: when the AMD-751 system controller is a target, it samples c/be[3:0]# on the rising edge of every pclk. c/be[3:0]# are qualified by frame# for commands and qualified by irdy# and trdy# for data. c/be[3:0]# are floated during reset# and when there is no initiator driving the bus. 4.2.3 devsel# (pci device select) bidirectional summary the AMD-751 system controller samples devsel# when it is the initiator in a pci cycle to determine if the target device has responded. the AMD-751 drives devsel# when it is the targeted device in a pci cycle. driven, sampled, and floated as an output: the AMD-751 system controller drives this signal when it decodes the address and determines it is the target of the transfer. as an input: when the AMD-751 system controller is the initiator, it samples this signal on the rising edge of every pclk to determine that the target is present. the target must respond within eight clocks after frame# is asserted. devsel# is floated during reset# and when there is no initiator driving the bus.
24 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.2.4 frame# (pci cycle frame) bidirectional summary the AMD-751 system controller asserts frame# at the beginning of a pci cycle when it is the initiator, and holds it asserted until the beginning of the last data transfer in the cycle. if the AMD-751 is the targeted pci device, it samples and latches the c/be[3:0]# and ad[31:0] signals and asserts devsel# at the first pclk edge on which it samples frame# asserted. driven, sampled, and floated as an output: the AMD-751 system controller drives frame# valid off the rising edge of pclk. the duration of frame# varies with the length of the transfer. as an input: when the AMD-751 system controller is a target, it samples this signal on the rising edge of every pclk. the assertion of frame# indicates the start of a cycle. frame# remains asserted during burst transfers. frame# is floated during reset# and when there is no initiator driving the bus. 4.2.5 gnt[4:0]# (pci bus grant) output summary as the pci bus arbiter, the AMD-751 system controller asserts one of these device-specific bus grant signals off the rising clock edge to indicate to an initiator that it has been granted control of the pci bus. driven gnt[4:0]# signals are never floated. they are negated off the rising edge of the clock, indicating that no device has been granted the bus. one of the gnt[4:0]# signals is asserted off the rising edge of the clock, indicating the particular channel that is granted use of the bus.
chapter 4 signal descriptions 25 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.2.6 irdy# (initiator ready) bidirectional summary irdy# indicates that a pci initiator is ready to complete the current data phase of the transaction. during a read cycle, irdy# asserted indicates the master is ready to accept the data. during a write cycle, irdy# asserted indicates that write data is valid on ad[31:0]. data is transferred on the pci bus on each pclk in which both irdy# and trdy# are asserted. wait states are inserted on the bus until both irdy# and trdy# are asserted together. driven, sampled, and floated as an output: when the AMD-751 system controller is the pci initiator, it drives irdy# asserted one pclk after it asserts frame# and holds it asserted until one cycle before the end of all transactions. the AMD-751 does not terminate a read or write cycle until it samples both irdy# and trdy# asserted. as an input: irdy# is sampled on every rising edge of pclk, when the AMD-751 system controller is a pci target. when irdy# and trdy# are both asserted, the controller advances the fifo to the next data. if either signal is negated, the current data is held on the bus. irdy# is floated when there is no bus master currently driving the bus. 4.2.7 lock# (pci bus lock) bidirectional summary a pci initiator asserts lock# to prevent other devices from accessing a targeted device during atomic transactions. using lock# is not recommended because it is not supported by the AMD-751 system controller, and the system can hang if the initiator does not unlock the resource. driven, sampled, and floated an 8.2-kohm pullup resistor is required to keep lock# inactive, if it is not implemented on an initiator.
26 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.2.8 par (pci bus parity) bidirectional summary par indicates even parity. the AMD-751 system controller drives par as a pci initiator one clock after the address phase and each data write phase to generate even parity across a_ad[31:0] and a_c/be[3:0]#. the AMD-751 drives par as a pci target one clock after each data read phase. the AMD-751 does not support parity checking. driven, sampled, and floated as an output: this signal is asserted off the rising edge of every pclk. as an input : the AMD-751 system controller does not support parity checking. par is only floated when changing bus ownership from one initiator to another. 4.2.9 pclk (pci clock) input summary pclk is a 33-mhz clock provided by the system clock generator. it is used by the AMD-751 logic in the pci clock domain. pclk to a_clk (agp clock) skew is +/ ? 500ps maximum. 4.2.10 pgnt# (pci grant to peripheral bus controller) output summary pgnt# grants control of the pci bus to the pci-isa/ide bridge functions implemented in the amd-756 peripheral bus controller. driven pgnt# is driven off the rising edge of pclk. reset# forces pgnt# inactive. pgnt# is asserted in response to a preq#.
chapter 4 signal descriptions 27 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.2.11 preq# (pci request from peripheral bus controller) input summary the AMD-751 system controller samples preq# to determine if the amd-756 peripheral bus controller needs pci bus access. sampled this signal is sampled by the rising edge of every pclk. if asserted, the arbiter issues a pgnt# when the bus is available. 4.2.12 req[4:0]# (pci bus request) input summary as the pci bus arbiter, the AMD-751 system controller samples these device-specific bus request signals to determine if another agent requires control of the pci bus. sampled these signals are sampled by the rising edge of every pclk. if active, the arbiter issues the corresponding gnt[4:0]# when the bus is available. 4.2.13 reset# (reset) input summary asserting reset# resets the AMD-751 system controller and sets all register bits to their default values. bidirectional signals are three-stated and outputs are driven inactive. this signal is driven by the pcirst# signal from the amd-756 peripheral bus controller. sampled this signal may be asynchronous to sysclk and pclk. it is synchronized internally, therefore it must be active for a minimum of four pclk periods.
28 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.2.14 serr# (system error) output summary the AMD-751 system controller, as a pci agent, asserts serr# off the rising edge of pclk one clock after it detects a system error. serr# is an input to the amd-756 peripheral bus controller, which can be programmed to generate a non-maskable interrupt (nmi). driven and floated serr# is driven asserted on the rising edge of pclk to indicate that a fatal condition has been detected by the AMD-751 system controller. this is an open-drain output ? normally a pullup resistor keeps this signal negated. 4.2.15 stop# (pci bus stop) bidirectional summary as a pci initiator, the AMD-751 system controller samples stop# to determine if the target device requires it to abort or retry a transaction. sampled stop# is sampled by the current initiator on the rising edge of every pclk to determine if the current transaction should continue or be stopped. 4.2.16 trdy# (target ready) bidirectional summary as a pci initiator, the AMD-751 system controller samples trdy# to determine when the target agent is able to complete the data phase of a transaction. as a pci target, the AMD-751 asserts trdy# to indicate that it has latched the data on ad[31:0] during a write phase or driven the data on ad[31:0] during a read phase. driven, sampled, and floated as an output: when the AMD-751 system controller is the pci target, it asserts trdy# when valid data is available on the bus (initiator read) or when there is room in its internal fifo
chapter 4 signal descriptions 29 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information (initiator write). the AMD-751 does not terminate a read or write cycle until it samples both irdy# and trdy# asserted. as an input: trdy# is sampled on every rising edge of pclk when the AMD-751 system controller is a pci initiator. when irdy# and trdy# are both asserted, the controller advances the fifo to the next data. if either signal is negated, the current data is held on the bus. trdy# is floated when there is no bus master currently driving the bus. 4.2.17 wsc# (write snoop complete) bidirectional summary wsc# is asserted to indicate that all of the snoop activity on the processor bus on behalf of the last pci-to-dram write transaction is complete and that an apic interrupt message can be sent. this signal is used only in configurations where an i/o apic is installed. driven and floated wsc# is driven asserted on the rising edge of pclk to indicate to the amd-756 peripheral bus controller that all probes due to pci dma (direct memory access) are complete. the amd-756 peripheral bus controller requests that the AMD-751 system controller issue a fence command to its buffers by placing a single pclk pulse on wsc#. the AMD-751 then marks the data currently in its buffers and waits for this data to reach processor-accessible (coherent) space. when this data reaches processor-accessible space, the AMD-751 responds by sending a two-clock pulse back to the amd-756 peripheral bus controller. after this pulse is received, the amd-756 peripheral bus controller transmits the interrupt message over the interrupt message bus (imb).
30 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.3 dram interface signals 4.3.1 cs[5:0]# (chip selects) output summary cs[5:0]# function as chip select signals for sdrams. driven these signals are negated by reset#. the memory controller asserts or negates these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information. 4.3.2 dqm[7:0]# (data mask) output summary dqm[7:0]# provides data masks for each byte during sdram write cycles. driven these control signals are negated by reset#. the memory controller asserts or negates these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information. 4.3.3 mada[14:0] and madb[14:0] (memory address) output summary the multiplexed row and column address bits mada[14:0] and madb[14:0] connect to the system sdrams. they can address any size dram from 4 mbits to 128 mbits (for example, 16 mbits x 4 = 64 mbits, 16 mbits x 8 = 128 mbits). two identical sets of memory addresses are provided to reduce signal loading for motherboard designs with three dimm slots. driven the memory controller asserts or deasserts these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information.
chapter 4 signal descriptions 31 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.3.4 mcke[2:0] (sdram clock enable) output summary mcke[2:0] are clock enable signals for the synchronous dram. they operate in parallel to drive greater loads than a single signal can support and are used for power saving modes. driven these control signals are driven inactive (negated) by reset#. see chapter 5, ? functional operation ? starting on page 45 for more information. 4.3.5 mdat[63:0] (memory data) bidirectional summary mdat[63:0] connect to the dram data i/o. they are driven by the dram during reads and are driven by the AMD-751 system controller during writes. driven, sampled, and floated as outputs: these signals are driven with the data to be written on the rising edge of sdram_clkout. the data changes at different times based on the type of memory and timing selected. see chapter 5, ? functional operation ? starting on page 45 for more information. as inputs: mdat[63:0] are sampled on the rising edge of sdram_clkin. mdat[63:0] are floated when neither the AMD-751 system controller or the memory are driving the bus.
32 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.3.6 meccd[7:0] (memory ecc) bidirectional summary meccd[7:0] carry error correction codes for the eight bytes of data on mdat[63:0]. these signals are inputs to the AMD-751 system controller during dram read cycles and outputs during dram write cycles. driven, sampled, and floated as outputs: these signals are driven with the parity or ecc data on the rising edge of sysclk. they change at different times based on the type of memory and timing selected. see chapter 5, ? functional operation ? starting on page 45 for more information. as inputs: meccd[7:0] are sampled on the same rising edge of sysclk that samples mdat[63:0]. meccd[7:0] are floated when neither the AMD-751 system controller or the memory are driving the bus. 4.3.7 scas[2:0]# (sdram column address strobes) output summary scas0#, scas1#, and scas2# are column address strobe signals for the synchronous dram. they operate in parallel to drive greater loads than a single signal can support. driven these control signals are driven inactive (negated) by reset#. the memory controller asserts or negates these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information. 4.3.8 sdram clk_in input summary the sdram clk_in signal is used to clock in the data returned from a sdram read operation. data is clocked in on the rising edge of this signal. this clock is provided by the zdb and is phase aligned with the sdram clocks.
chapter 4 signal descriptions 33 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.3.9 sdram clk_out output summary sdram clk_out is a clock signal for the synchronous dram. driven this signal is a free-running clock generated by the internal pll in the AMD-751 system controller. this signal is used to clock a zero delay buffer (zdb) external to the AMD-751. the zdb, in turn, generates the clock for the sdrams. the advantage of the zdb is that the timing of the clocks to the sdram dimms can be adjusted. 4.3.10 sras[2:0]# (sdram row address strobes) output summary sras0#, sras1#, and sras2# are row address strobe signals for the synchronous dram. they operate in parallel to drive greater loads than a single signal can support. driven these control signals are driven inactive (negated) by reset#. the memory controller asserts or negates these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information. 4.3.11 we[2:0]# (sdram memory write enables) output summary we[2:0]# are write enable signals for all dram. they operate in parallel to drive greater loads than a single signal can support. driven these control signals are driven inactive (negated) by reset#. the memory controller asserts or negates these signals off the rising edge of sysclk at the appropriate time in the memory access sequence. see chapter 5, ? functional operation ? starting on page 45 for more information.
34 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.4 agp/pci signals the following signal descriptions apply to agp bus signals when used for agp transactions. the agp bus can also perform pci transactions, in which case the agp bus pins function identically to their pci bus pin equivalents (same pin names without the a_ prefix), as described in ? pci interface signals ? on page 22. 4.4.1 a_ad[31:0] (address/data bus) bidirectional summary in multiplexed mode, the a_ad[31:0] bus contains an agp address when pipe# is sampled asserted and data when pipe# is sampled negated. in demultiplexed mode, the a_ad[31:0] bus contains only agp data, while agp addresses are provided on the sideband address signals sba[7:0]. driven, sampled, and floated as outputs: in demultiplexed mode, the AMD-751 system controller drives a_ad[31:0] with adstb[1:0] during data transfers to the graphics controller from the system controller. in multiplexed mode, the AMD-751 drives a_ad[31:0] with a valid address or data off the rising edge of sysclk during the return of read requests. in addition, a_ad[31:0] are driven during processor writes to the graphics controller. as inputs: in demultiplexed mode, the AMD-751 system controller samples a_ad[31:0] on the rising edge of every adstb[1:0] during data transfers from the graphics controller to the system controller. in multiplexed mode, a_trdy# and a_irdy# qualify the sysclk edges on which data is sampled. a_ad[31:0] are floated for one clock between the address phase and the data phase of a read transfer. in addition, a_ad[31:0] are floated during reset and when the bus is idle.
chapter 4 signal descriptions 35 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.4.2 a_c/be[3:0]# (pci command/byte enables) bidirectional summary in multiplexed mode, a_c/be[3:0]# contain command information when pipe# is sampled asserted (see page 40), and byte-enable signals when pipe# is sampled negated. for pci cycles on the agp bus, c/be#[3:0] carry pci commands during the first clock cycle that a_frame# is asserted. after the first clock, a_c/be[3:0]# are byte enables. in demultiplexed mode, the commands are sent on sba[7:0], and a_c/be[3:0]# function only as byte enable signals during data transactions. all four a_c/be# signals are asserted in each agp data transaction because the minimum agp data size is four doublewords. driven, sampled, and floated as outputs: the AMD-751 system controller drives a_c/be[3:0]# with valid command information off the rising edge of sysclk when a_frame# or pipe# is asserted. the AMD-751 drives a_c/be[3:0]# with valid byte enables off the rising edge of sysclk when a_frame# or pipe# is negated. as inputs: when the AMD-751 system controller is a target, it samples a_c/be[3:0]# on the rising edge of sysclk. a_c/be[3:0]# are floated during reset and when the bus is idle. 4.4.3 a_clk (agp clock) input summary a_clk receives a 66-mhz clock from the system clock generator. a_clk is used by the AMD-751 system controller logic in the agp clock domain.
36 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.4.4 a_devsel# (pci device select) bidirectional summary a_devsel# is used for pci transfers on the secondary pci bus. its function is the same as that of devsel# on the primary pci bus (see page 23). a_devsel# is not used during agp transfers. 4.4.5 a_frame# (pci cycle frame) bidirectional summary a_frame# is used for pci transfers on the secondary pci bus. its function is the same as that of frame# on the primary pci bus (see page 24). a_frame# is not used during agp transfers. 4.4.6 a_gnt# (agp bus grant) output summary as the agp bus arbiter, the AMD-751 system controller asserts a_gnt# in response to a_req# from the initiator (graphics controller) to indicate to the initiator that it has been granted control of the bus. at the same time, the system controller provides status information on status signals st[2:0] to indicate to the initiator whether it is to supply data or receive data in response to a previously queued request. driven a_gnt# is asserted off the rising edge of sysclk in response to an a_req#. a reset forces a_gnt# to be negated.
chapter 4 signal descriptions 37 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.4.7 a_irdy# (initiator ready) bidirectional summary as a target, the AMD-751 system controller samples a_irdy# to look for the beginning of a write transfer from the initiator to determine if the initiator is ready to transfer a block. for an agp write transfer, all data in the given transaction is sent without wait-states, so a_irdy# only needs to be sampled once for the entire transaction. an agp read transfer can have wait-states, so the AMD-751 must sample a_irdy# asserted for each block of a read transfer. a block is the amount of data transferred in four sysclk cycles ? four doublewords in 1x mode and eight doublewords in 2x mode. as an initiator, the AMD-751 system controller asserts a_irdy# to signal the agp device that it is ready to begin a transfer. note: because a_frame# is not used in an agp transaction, there is no relationship between a_frame# and a_irdy#, as there is in a pci transaction. driven, sampled, and floated as an output: the AMD-751 system controller drives a_irdy# valid off the rising edge of sysclk. for agp transfers, a_irdy# is asserted for one clock. for pci transfers, it is driven during the entire transaction. as an input: when the AMD-751 system controller is a target, it samples a_irdy# on the rising edge of sysclk. for agp transfers, a_irdy# is sampled only at the beginning of a cycle. a_irdy# is floated during reset and when there is no initiator driving the bus. 4.4.8 a_par (pci bus parity) bidirectional summary a_par# is used for pci transfers on the secondary pci bus. its function is the same as that of par# on the primary pci bus (see page 26). a_par# is not used during agp transfers.
38 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.4.9 a_req# (agp bus request) input summary as the bus arbiter, the AMD-751 system controller monitors a_req# to determine if the graphics controller requests access to the agp bus. if a_req# is sampled asserted, the arbiter asserts a_gnt# as soon as the bus is available. sampled a_req# is sampled on the rising edge of every sysclk. 4.4.10 a_serr# (system error) input summary a_serr# is used for pci transfers on the secondary pci bus. it is not used during agp transfers. 4.4.11 a_stop# (agp bus stop) bidirectional summary a_stop# is used for pci transfers on the secondary pci bus. its function is the same as that of stop# on the primary pci bus (see page 28). a_stop# is not used during agp transfers. 4.4.12 a_trdy# (target ready) bidirectional summary as an agp target, the AMD-751 system controller asserts a_trdy# to signal the start of a read or write data block transfer. a block is the amount of data that can be passed in four sysclk cycles ? four doublewords in 1x mode, eight doublewords in 2x mode. if a transfer is larger than one block, a_trdy# must be reasserted for each block. asserting a_trdy# every four clock cycles completes the transfer without wait states. as an agp initiator, the AMD-751 samples a_trdy# to determine if data is ready to be transferred.
chapter 4 signal descriptions 39 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information driven, sampled and floated as an output: the AMD-751 system controller drives a_trdy# valid off the rising edge of sysclk. in agp-multiplexed mode, data remains on the bus until a_trdy# is asserted. in agp-demultiplexed mode, a_trdy# is asserted for one clock for each block transferred. as an input: when the AMD-751 system controller is an initiator, it samples a_trdy# on the rising edge of sysclk. for agp transfers, a_trdy# is sampled only at block boundaries. a_trdy# is floated during reset and when there is no target driving the bus.
40 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.5 agp-only signals 4.5.1 adstb[1:0] (ad bus strobe) bidirectional summary in 2x mode, adstb0 provides timing for a_ad[15:0] and adstb1 provides timing for a_ad[31:16]. the graphics controller drives the strobes during agp write operations, and the AMD-751 system controller drives them during agp read operations. adstb[1:0] serves as a source-synchronized strobe when transferring data in demultiplexed mode. this signal is essentially a copy of the clock that is synchronized to the data. this source-synchronized technique minimizes skew between the strobe and data and compensates for propagation delay. in 1x mode, adstb[1:0] is ignored while sysclk is used. driven, and floated as an output: a_ad[31:0] and adstb[1:0] are both synchronous to sysclk. when the AMD-751 system controller is an initiator, it uses the rising and falling edges of adstb0 to clock data into the target. as an input: when the AMD-751 system controller is a target, it uses the rising and falling edges of adstb[1:0] to clock data into its internal registers. adstb[1:0] is floated during reset and when there is no device driving the bus. 4.5.2 pipe# (apg pipeline) input summary the assertion of pipe# indicates the beginning of a new bus cycle. the AMD-751 system controller queues a request from the initiator on each rising clock edge on which it samples pipe# asserted. when pipe# is sampled negated, no new requests are queued. sampled the AMD-751 system controller samples pipe# on the rising edge of every sysclk.
chapter 4 signal descriptions 41 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.5.3 rbf# (read buffer full) input summary an agp initiator asserts rbf# to indicate that its buffers are full. as an agp target, the AMD-751 system controller cannot commence a low priority data read to the initiator until it samples rbf# negated. rbf# does not apply to high-priority read data. sampled the AMD-751 system controller samples rbf# on the rising edge of sysclk before initiating a low-priority read data transfer. 4.5.4 sba[7:0] (sideband address bus) input summary in agp demultiplexed mode, the AMD-751 system controller receives address and command signals from sba[7:0] rather than a_ad[31:0] and a_c/be[3:0]#. in agp multiplexed mode, sba[7:0] are ignored. sampled the AMD-751 system controller samples sba[7:0] using the sbstb signal. in 1x mode, the rising edge of sysclk strobes in the commands on sba[7:0]. in 2x mode, both edges of sbstb strobe in commands on sba[7:0]. an ffh on these signals is a nop (no operation).
42 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 4.5.5 sbstb (sideband strobe) input summary sideband strobe is a synchronization clock generated by the agp initiator for sba[7:0] in 2x mode. the AMD-751 system controller uses sbstb to strobe in commands on the sba bus to its request queue. sbstb is driven continuously by the graphics device ? nops are strobed when no command is present. the AMD-751 strobes in commands on the rising edge of sysclk in 1x mode and both rising and falling edges of sbstb in 2x mode. 4.5.6 st[2:0] (status) output summary as the agp arbiter, the AMD-751 system controller drives st[2:0] when it asserts a_gnt# to inform the graphics controller of the type of data being returned, or that the AMD-751 is ready to accept a command. driven st[2:0] are asserted off the rising edge of sysclk. reset forces st[2:0] to be negated (bus-available state).
chapter 4 signal descriptions 43 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 4.6 miscellaneous signals 4.6.1 rom_sck (srom clock) bidirectional summary rom_sck drives the clk pin of the debug srom. if this signal is pulled high during reset#, the srom supplies the sip packet. if this signal is pulled low, the sip packet is generated internal to the AMD-751 system controller. 4.6.2 rom_sda (srom data) bidirectional summary rom_sda connects to the data pin of the debug srom. 4.6.3 scan_en# (scan enable) input summary when scan_en# is asserted, the internal scan chains are enabled. scan chain heads and tails are multiplexed from functional pins. this signal has an internal pullup resistor. 4.6.4 tristate# input summary when tristate# is asserted, all outputs are floated and the nand tree is enabled. this signal has an internal pullup resistor.
44 signal descriptions chapter 4 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information
chapter 5 functional operation 45 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5 functional operation this section details the operation of the AMD-751 system controller. 5.1 system addressing overview the AMD-751 system controller supports the amd athlon system bus specification. the amd athlon processor contains mapping logic for all legacy x86 addresses through an address map (see table 7 on page 46). as shown in figure 5, legacy x86 (ibm pc-at) memory mappings are implemented on the amd athlon processor. figure 5. system memory view amd athlon ? family x86 processor pc memory view mapping logic amd athlon system bus northbridge (AMD-751 ? ) southbridge (amd-756 ? ) pci
46 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information address map table 7 shows the AMD-751 system controller address map. table 7. AMD-751 ? system controller memory address map address space start address space end name/command description pa msb =0 and 1 ff00 0000 pa msb =0 and 3 ffff ffff reserved (masked) reserved for use by the AMD-751 system controller. pa msb =0 and 1 fe00 0000 pa msb =0 and 1 feff ffff pci configuration space (masked) this space is used to create pci configuration cycles using wrbytes, wrlws, rdbytes, and rdlws commands only. see ? pci configuration ? on page 79. pa msb =0 and 1 fc00 0000 pa msb =0 and 1 fdff ffff pci i/o space (masked) this space is used to create pci i/o cycles using wrbyteswrlws, rdbytes, and rdlws commands only. pa msb =0 and 1 f800 0000 pa msb =0 and 1 fbff ffff pci iack/special cycle generation (masked) wrlws commands to this space are used to create pci special cycles. the lower 32 bits of the data are passed on to the pci bus as both the address and data with the special-cycle pci command. see table 8 on page 48 for all special cycles generated by the processor. rdbytes commands to this space are used to create pci iack. the lower 16 bits of these addresses are passed on to the pci unmodified with the iack pci command. see ? pci configuration accesses ? on page 50. pa msb =0 and 1 0000 0000 pa msb =0 and 1 f7ff ffff reserved (masked) reserved for use by the AMD-751. pa msb =0 and 0 0000 0000 pa msb =0 and 0 ffff ffff pci memory space (masked) the lower 32-bits of these addresses are forwarded, unmodified, to the pci and are accessed with wr/rdbytes, wr/rdlws, or wr/rdqws only. the AMD-751 generates low-order address bits required by the amd athlon system bus mask field. pa msb =1 and 0 0000 0000 pa msb =1 and 3 ffff ffff normal memory (masked writes) dram, accessed with masked write commands wrbytes, wrlws, and wrqws only. pa msb =1 and 0 0000 0000 pa msb =1 and 3 ffff ffff reserved (masked reads) the AMD-751 does not support masked reads to this address space. pa msb =1 and 0 ff000 0000 pa msb =1 and 3 ffff ffff reserved (blocks) this address space can be used by the AMD-751 for undefined purposes. pa msb = 0 and 0 0000 0000 pa msb = 0 and 3 ffff ffff normal memory (blocks) dram, accessed with read and write block commands. note: the AMD-751 only uses 32 address bits internally and the address space wraps. address 1 0000 0000 is treated the same as 0 0000 0000. note: msb = most significant bit
chapter 5 functional operation 47 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 6 shows the x86 view of memory from the perspective of the amd athlon processor, and mapping to the amd athlon system bus memory map. figure 6. address mapping for x86 legacy top-of-memory (tom) vga dos memory x86 memory address space amd athlon ? system bus address space apic registers pci memory reserved agp virtual reserved extended memory gart bios (bar0) pci config reserved pci iack/special pci i/o memory pci memory 0cf8h, 0cfch i/o space x86 in and out address space f_ffffh a_0000h
48 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information special cycles there are seven special cycles generated by the amd athlon processor that are passed onto the pci bus with specific values in the address and data fields of the pci special cycle command. table 8 defines these values (same value for address and data). table 8. amd athlon ? processor special cycle encoding special cycle pci address and data field contents processor description AMD-751 ? and amd-756 ? description shutdown 0000 0000 the amd athlon generates this special cycle in response to a shutdown condition. the amd athlon system bus issues a wrlws command with pa = speccycbase and sdata[31:0] = 0000_0000h. note: speccycbase is msb=0 and pa[33:0] = 1 f800_0000h. the AMD-751 forwards onto the pci bus a pci special cycle command with ad[31:0] = 0000_0000h (address and data). the amd-756 asserts init to the processor. halt 0000 0001 the amd athlon generates this special cycle in response to a halt instruction. the amd athlon system bus issues a wrlws command with pa = speccycbase and sdata[31:0] = 0000_0001h. the AMD-751 waits for all queues to memory to be empty (assumes the pci grant-enable register is clear, device 0, offset 84). the AMD-751 optionally (through offset 60, bit 18) initiates an amd athlon system bus disconnect to the processor. the AMD-751 forwards onto the pci bus (after the optional amd athlon system bus disconnect) a pci special cycle command with ad[31:0] = 0000_0001h (address and data). the amd-756 ignores this cycle. wb invalidate 0001 0002 the amd athlon generates this special cycle in response to executing a wbinv instruction. the amd athlon system bus issues a wrlws command with pa = speccycbase and sdata[31:0] = 0001_0002h. the AMD-751 forwards a pci special cycle command onto the pci bus with ad[31:0] = 0001_0002h (address and data). the amd-756 ignores this cycle.
chapter 5 functional operation 49 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information invalidate 0002 0002 the amd athlon generates this special cycle in response to executing an invd instruction. the amd athlon system bus issues a wrlws command with pa = speccycbase and sdata[31:0] = 0002_0002h. the AMD-751 forwards a pci special cycle command onto the pci bus with ad[31:0] = 0002_0002h (address and data). the amd-756 ignores this cycle. flush ack 0003 0002 the amd athlon generates this special cycle in response to assertion of the flush pin after all caches have been flushed to memory. the amd athlon system bus issues a wrlws command with pa = speccycbase and sdata[31:0] = 0003_0002h. the AMD-751 forwards a pci special cycle command onto the pci bus with ad[31:0] = 0003_0002h (address and data). the amd-756 ignores this cycle. connect 0004 0002 the amd athlon generates this special cycle as the first cycle after a stop grant or halt system bus special cycle. the connect cycle is issued by the processor regardless of whether a disconnect was achieved. pa = speccycbase and sdata[31:0] = 0004_0002h. the AMD-751 forwards a pci special cycle command onto the pci bus with ad[31:0] = 0004_0002h (address and data). the amd-756 ignores this cycle. stop grant 0012 0002 the amd athlon generates this special cycle in response to assertion of stpclk#. the amd athlon system bus issues a wrlws command pa = speccycbase and sdata[31:0] = 0012_0002h. the AMD-751 waits for all queues to memory to be empty (assumes the pci grant-enable register is clear, device 0, offset 84). the AMD-751 optionally (through device 0, offset 60, bit 17) initiates an amd athlon system bus disconnect to the processor. the AMD-751 forwards onto the pci bus (after the optional amd athlon system bus disconnect) a pci special cycle command ? ad[31:0] = 0012 0002 (address and data). the amd-756 receives and enters the appropriate power state. the amd-756 can then assert dcstop# to the AMD-751 to signal that it should deassert mcke to the sdrams and stop its internal clocks. table 8. amd athlon ? processor special cycle encoding (continued) special cycle pci address and data field contents processor description AMD-751 ? and amd-756 ? description
50 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information pci configuration accesses in legacy x86 pc systems, pci configuration cycles are generated by an indirect method. a configuration address register defined at i/o address 0cf8h allows the software to load a 24-bit value that is asserted on the pci address lines during the next configuration read/write cycle. a configuration data register defined at i/o address 0cfch allows the software to generate configuration read and write cycles on the pci using in and out instructions. data sent to the configuration data register during out instructions is driven on the pci data lines during the configuration write transaction. data received in response to a configuration read transaction is returned to satisfy the in from the configuration data register. in amd athlon system bus systems, pci configuration cycles are generated by explicitly using rdbytes/rdlws and wrbytes/wrlws commands to a 16-mbyte region at address 1f-e000-0000h, as shown in figure 6 on page 47. the x86 processor must detect in and out instructions that reference 0cf8h and 0cfch, and generate the appropriate rdbytes/rd/lws and wrbytes/wrlws amd athlon system bus commands. command address decoding decoding logic in the AMD-751 processor and pci interfaces provides a consistent view of memory and pci devices. the AMD-751 considers the processor ? s request and physical address (pa) fields when decoding a command. this command address decoding is summarized as follows: n if pa msb = 0 and the command is a block command, dram is accessed. if pa[31:0] falls between device 0, bar0 and device 0, bar0+len, the address to agp virtual address space is passed through the gart before presentation to the dram. n if pa msb = 1 and the command is a masked write command (wrqws, wrlws, wrbytes), dram is accessed. if pa[31:0] falls between device 0, bar0 and device 0, bar0+len, the address to agp virtual address space is passed through the gart before presentation to the dram.
chapter 5 functional operation 51 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information n if pa msb = 0, pa[35:32] = 0, and the command is a masked command, a pci memory-mapped i/o cycle is performed. using device 0, offset 14h, bar1, the access is directed to AMD-751 memory mapped gart control registers (see chapter 7, ? configuration registers ? on page 123). using device 1, offset 20h and device 1, offset 22h, memory base and limit registers, the access is directed to either pci or agp/pci using address bits 31 ? 0. n if pa msb = 0, pa[35:24] = 1f8h, and the command is rdbytes, an iack special cycle is generated on the primary pci bus. pa[15:0] are driven on the pci ad[15:0] bus during this cycle. the data returned on the pci bus is returned to the processor. n if pa msb = 0, pa[35:24] = 1f8h, and the command is wrbytes, a pci special cycle is generated on the primary pci bus. pa[15:0] are asserted on the pci ad[15:0] lines during this cycle. n if pa msb = 0, pa[35:24] = 1fch or 1fdh, and the command is rdbytes or wrbytes, a pci i/o command is generated. pa[23:0] are driven on the pci ad[23:0] lines with the pci i/o read or write command. using device 1, offset 1ch and device 1, offset 1dh, i/o base and range registers, the access is directed to either the primary pci bus or the secondary pci bus. n if pa msb = 0, pa[35:24] = 1feh, and the command is rdbytes or wrbytes, a pci configuration command is generated. pa[23:0] are asserted on the pci ad[23:0] lines with the pci configuration read or write command. note: the low-order processor address bits of pa only go down to physical address pa[3]. for mask operations, the mask[7:0] bits are encoded to logically create pa[2:0].
52 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information pci/agp master address decoding to route a transaction, the pci controllers in the AMD-751 system controller compare the received pci/agp (secondary pci bus) address with the bar registers and the memory configuration registers. in addition, the AMD-751 decodes the amd athlon processor commands to properly direct pci traffic that references the legacy 640-kbyte to 1-mbyte memory range. this decoding is summarized as follows: n if ad[31:0] is less than the physical top-of-memory (from the memory controller), dram is accessed. n if ad[31:0] is above the physical top-of-memory and falls between device 0, bar0 and device 0, bar0+len, the address to the agp virtual address space needs to pass through the gart before presentation to dram. n if ad[31:0] is above the physical top-of-memory and falls between device 1, 30h memory range decoding register start and ending fields, the secondary pci bus is accessed (for writes only from the primary pci). n otherwise, the primary pci bus is accessed (for writes from the agp/pci bus only). note: the AMD-751 does not allow access to the memory-mapped gart control registers from either pci or agp/pci masters. for more information about the gart, see ? gart cache operation ? on page 98. configuration register access the AMD-751 system controller implements most registers as pci configuration registers. configuration accesses in the AMD-751 conform to the following rules: n the AMD-751 is defined to be device 0 and device 1. all external pci devices must be wired to one of the ad[31:13] wires. logically, ad[12:11] are assigned to devices 0 and 1 in the AMD-751 system controller. n device 0 accesses correspond to the processor-to-pci bridge registers defined in chapter 7, ? configuration registers ? on page 123. n device 1 accesses correspond to the pci-to-pci bridge registers defined in chapter 7, ? configuration registers ? on page 123. n accesses can have a byte, word, or doubleword length and must be naturally aligned.
chapter 5 functional operation 53 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.2 processor interface this section describes the interface logic between the amd athlon processor and the AMD-751 system controller. 5.2.1 bus interface unit (biu) the bus interface unit (biu) is the interface between the processor and the rest of the system. the biu receives commands and probe responses from the processor and issues probes to the processor. the biu initiates all data movement into and out of the processor. figure 7 shows a biu block diagram. figure 7. block diagram of the bus interface unit (biu) biu queues the biu contains the following queues: n the command queue (cq) receives transaction requests from the processor and stores them until they can be dispatched by the destination-dispatch agent. preprocessing block processor source synch clock transceiver probe response alert agent (pra) probe response from mro, memory done probe queue (pq) fully snoopable partial tag comp. issued probes probe sysdc queue (psq) xca from pci/a-pci probe done sysdc read queue (srq) to mro memory write queue (mwq) pci/a-pc i write queue (awq) pending probes queue (ppq) fully snoopable to pci/a-pci command queue (cq) ack csq
54 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information n the probe queue (pq) stores probes from the system to the processor. to maintain coherency, the pq is snoopable. n the processor system data and control queue (csq) stores system data control commands in three separate read and write buffers for data movement in and out of the processor caused by commands generated by the processor itself. n the probe system data and control queue (psq) stores system data control commands for data movement in and out of the processor for probes generated by the system. biu functional units the biu contains the following functional units: n the probe response alert agent (pra) broadcasts probe responses it receives from the processor. the probe response can come as a quick probe miss or no-data-movement-required commands, or it can come as a long probe-response command. n the transaction combiner agent (xca) is responsible for creating a command packet from the system to the processor containing sysaddout command format and probe information. the xca intelligently combines, when possible, the csq or psq entry and the pq entry, and transmits it to the processor using the four-cycle sysaddout command format. when there is either no pq entry, csq entry, or psq entry ready for dispatching, a nop is inserted by the combiner logic. the acknowledge (a-bit) information is also packed in the four-cycle sysaddout command format. 5.2.2 biu start-up the amd athlon system bus is a unique, source-synchronous, channel that uses protocol and fixed delivery windows to provide maximum performance. an amd athlon system bus is synchronous. however, the use of multiple plls in the system and the use of source-synchronous clocking create different clock domains from the processor to the system logic and from the processor to a backside l2 cache. a clock domain is the component or set of components running on one clock signal for its logic operation. for example, the AMD-751 system controller is one clock domain and operates on its own pll. although this pll is driven from the same clock generator as the rest of the system, drifts and skews in the
chapter 5 functional operation 55 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information internal clock place this device in a different clock domain than the processor. similarly, the processor has its own pll and, while synchronous, its own clock domain. when the processor and system logic transfer data back and forth, they send a source-synchronous clock with the data. in this way, the data can be received into input buffers using a clock that has a known, fixed relationship to the data. when data is received, special logic (fifos, counters, etc.) allows the data to be reliably moved from the clock domain of the transmitting device to the clock domain of the receiving device. to ensure efficient, reliable operation, and to know which clock edge has which data, this logic must be programmed for the component and board delays before any transfer can occur. the processor uses a packet-based protocol with predefined delays from protocol packets to data transfers. however, these delays are defined based on the processor clock frequency and certain programmable values. these values must be correctly programmed and agreed upon before any transfer can occur. as part of the reset sequencing, the processor and system logic use a set of shared interface pins (connect, clkfwdrst, and procrdy) to serially transfer a serial initialization packet (sip) from a rom table in the AMD-751 to the processor. resister strapping options on the amd athlon system bus card-edge connector select the entry in this rom table. the strapping tells the AMD-751 what speed and what processor type is in the processor module. for the appropriate entry in the table, the AMD-751 transmits a serial bit stream to the processor and uses other bits for its own state machines and logic. in this way, the processor and the AMD-751 establish a predefined set of operating assumptions and conditions. because the amd athlon system bus protocol is packet-based, the beginning of each packet must be negotiated between the sender and the receiver. this negotiation is accomplished by starting with an all 1b bit pattern (a nop command) until the first non-nop packet boundary is identified. from that point forward, simple counters can track the start of each packet. initially the processor issues a packet to the AMD-751, which marks the beginning of the packet. the AMD-751 responds with a packet that the processor uses to synchronize the return path. as long as the bus clocks continue to run, the packet-timing relationship remains valid.
56 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information serial initialization packet (sip) protocol the sip protocol is shown in figure 8 and described in table 9. for a typical system reset sequence, the amd-756 peripheral bus controller asserts pcirst# to the system reset input and cpurst# to the processor reset# input. figure 8. sip protocol table 9. sip protocol states and actions state action 1 when nb_reset# and reset# are asserted, the system asserts connect and clkfwdrst and the processor asserts procrdy. 2 when nb_reset# is deasserted, the system deasserts connect, but continues to assert clkfwdrst. when reset# is deasserted, the processor deasserts procrdy and is ready for initialization (through the sip protocol). note : the system must be out of reset before the processor deasserts procrdy. 3 one or more sysclk periods after the deassertion of procrdy, the system deasserts clkfwdrst. (states 3 and 4 are performed for amd athlon system bus legacy reasons.) 4 one or more sysclk periods after the deassertion of clkfwdrst, the system again asserts clkfwdrst. 5 either at the assertion of clkfwdrst or one or more sysclk periods later, the processor expects the start bit (connect asserted) of the sip. the system delivers the sip containing the processor source-synchronous initialization state over connect. after the sip is transferred, the system asserts and holds connect, which indicates the end of the sip transfer to the processor. 6 one or more sysclk periods after receiving the sip, the processor asserts procrdy to indicate to the system that it has received the sip, initialized itself, and is ready. start sip1 sipn cmd 0ns 25ns 50ns 75ns 100ns 125ns nb_reset# reset# clkfwdrst connect procrdy sysclk saddoutclk# addout[14:2]#
chapter 5 functional operation 57 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information amd athlon ? processor sip mapping. the AMD-751 system controller is responsible for supplying initialization values to the amd athlon processor that are a function of physical amd athlon system bus length, sysclk frequency, and processor clock multiplier. these values must be loaded prior to any amd athlon system bus transactions and are supplied through the sip protocol. the AMD-751 implements two modes ? production and debug. during reset, if rom_sck is pulled high (debug mode), the srom supplies the sip packet to the AMD-751. if rom_sck is pulled low (production mode), the sip packet is generated internally. 5.2.3 processor write posting the AMD-751 system controller contains two write buffers to enhance write performance. each buffer can hold four entire cache lines, also referred to as data blocks. each data block is 64 bytes (eight quadwords). the write buffers are always enabled. the memory controller supports both single writes and block writes. block writes are more common in a typical system than single writes because the processor uses writeback caches, which transfer data in blocks. when a writeback cache is employed, the AMD-751 sees a block transaction every time the processor clears a cache line. the posted write buffers of the AMD-751 can handle four back-to-back block transactions without wait states. figure 9 on page 58 shows the organization of the posted write buffers. 7 one or more sysclk periods after the assertion of procrdy, the system deasserts clkfwdrst. 8 three sysclk periods after clkfwdrst deassertion, the processor drives its source-synchronous clocks. the processor indicates bit-time 0 to the system by issuing a non-nop command on the appropriate source-synchronous clock. table 9. sip protocol states and actions (continued) state action
58 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 9. amd athlon ? system bus data buffers (biu) the write buffers are organized as pseudo first-in-first-out (fifo) buffers. that is, writes from the buffers to memory are usually performed in the order they are received from the processor. four consecutive write transactions, whether single or block, fill all four 64-byte buffers. write buffers continue to accept data until either the buffers are full or all data from the processor is received. at that point, the AMD-751 begins writing data to the dram. as each pending write to main memory is performed, freeing the corresponding buffer, the memory controller sends a command to the processor. 5.2.4 read buffer the AMD-751 system controller contains two, 64-byte by four-entry read buffers. each buffer can hold an entire block of data. memory reads that fill the processor caches are by far the most common types of reads. these reads occur as a burst read of eight quadwords (64 bytes). the read buffers snoop write transactions to maintain data coherency. if a write transaction occurs to an address where one of the read buffers contains data, that read buffer is invalidated. memory read data buffer 64 bytes x 4 entries to the processor from the processor command select pci/a-pci read data buffer 64 bytes x 2 entries probe data movement buffer 64 bytes x 4 entries pci/a-pci write data fifo 8 bytes x 12 entries memory write data buffer 64 bytes x 4 entries
chapter 5 functional operation 59 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.3 memory interface the AMD-751 system controller memory interface contains two functional blocks ? the memory request organizer (mro), which serves as a data crossbar and kernel for the AMD-751, and the memory controller (mct), which is designed to operate up to three pc-100 sdram dimms. 5.3.1 memory request organizer (mro) the memory request organizer (mro) is responsible for scheduling read/write requests to main memory from the biu, primary pci, and secondary a-pci (agp). the mro evaluates all the dependencies a particular read/write request may have, waits for all these dependencies to resolve, and routes the data accordingly. the mro consists of the following modules: n memory queue arbiter (mqa) n four memory read queues (mrq[3:0]) n memory write queue (mwq) n memory write selector (mws) a top-level diagram of the mro is shown in figure 10 on page 60.
60 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 10. memory request organizer (mro) block diagram memory queue arbiter (mqa) the memory queue arbiter (mqa) is responsible for choosing between read and write requests from all sources (biu, pci, and a-pci) in a round-robin (rbn) manner. the mqa sends one read or write transaction to the mrqs or mwq on each clock cycle. in addition, the arbiter performs translation from the physical address to the dram bank/row/column address, based on the dram socket addressed in a request. a two-level prioritization scheme is used. at the highest level there are two requesters ? the biu and all other requesters or ? ed together. the second level of the hierarchy contains a round-robin arbiter between the peripheral requesters. figure 11 on page 61 shows the structure of this arbiter. agp requests undergo address translation in the mro and are forwarded directly to the mct. from biu memory queue arbiter (mqa) from pci from a-pci mws to mct mrq3 mrq2 mrq1 mrq0 from agp agp address translator (aat) rbn mwq
chapter 5 functional operation 61 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information the output from the mqa is passed on to one of the mrqs or the mwq, to be scheduled by the memory request scheduler (mrs) as described in the ? memory controller (mct) ? on page 63. the mrs is responsible for scheduling requests from various sources onto the actual memory interface. figure 11. memory queue arbiter (mqa) block diagram the arbiter is disabled if there are no free entries in the mrqs or mwq. all requests are held until some of the older requests in the full queue are serviced. however, if one of the queues has available entries, the arbiter continues to issue requests to it, even if the other queue is stalled. the memory read queues (mrq) the four memory read queues (mrq) store four read requests, each directed to the main memory (with the exception of agp read requests, which bypass the read queue). each mrq holds read requests for one of the four banks of memory. each entry contains transfer-relevant information, such as address and size, as well as dependency flags. the flags are cleared when the dependencies are removed. a read-request entry is placed in the mrq by the mqa. the new request is entered on top of the latest request in the queue, unless the request is a page hit (ph). in the case of a page hit, the request is placed ahead of any page-miss requests, but behind any older page-hit requests. therefore, the queue is built with the oldest page-hit request at the bottom of the queue and the newest page miss at the top. the rbn schedules the read request to the mct in a round-robin manner. two-input round-robin arbiter first-level of arbiter request three-input round-robin arbiter top-level of arbiter biu request pci request a-pci request force priority
62 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information when the entry is put into the mrq, the address of the read request is passed through the memory write queue (mwq) and compared with all valid mwq entries. if one or more write requests in the mwq are pending to the same cache line addressed by the read request, a dependency exists and this particular read request cannot be scheduled by the mrs until the writes have completed. memory write queue (mwq) the memory write queue (mwq) stores six write requests directed to main memory. each entry contains transfer-relevant information, such as address and size, as well as dependency flags. the flags are cleared when the dependencies are removed. when the entry is put into the mwq, the address of the write request is compared with all current entries in the mwq. if one or more write requests in the mwq are pending to the same cache line addressed by the new write request, the dependent writes are executed in order. memory write selector (mws) the memory write selector (mws) chooses one eligible write to present to the mct. the write that is chosen is the oldest entry that has resolved all of its data dependencies. in addition, the module contains logic to correctly sequence a merged write to the mct, which occurs when a partial cache line write results in a processor probe data movement. the processor data is written to memory first, followed by the partial cache line data. both writes originate from a single mwq entry, presented back-to-back by the mws. agp read/write requests are handled in a slightly different manner than the other requests. agp requests have address translation applied in the mro, and then the requests are forwarded to the mct. the mro forms a fully-coherent subsystem. to determine any dependencies, all read requests entering the read queue cause a probe to all pending write requests in the write queue. if a dependency is detected, the read is not sent to memory until the write is serviced. likewise, all write requests entering the write queue are compared with existing entries to see if dependencies exist. if a dependency is found, the dependent writes are executed in order.
chapter 5 functional operation 63 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.3.2 memory controller (mct) the memory controller (mct) arbitrates and optimizes incoming memory requests, handles ecc and graphics address remapping table (gart) walks (gtw), gathers and retrieves data, and controls up to three sdram modules or six banks. bank one is enabled by cs[0]#, bank two is enabled by cs[1]#, and so on. single-banked memory modules require one cs[5:0]# signal. dual-banked memory modules occupy two rows of memory and require one sras# and two cs[5:0]# signals. dram banks are grouped into three pairs. each pair can have zero, one, or both banks populated. see figure 13 on page 67 for more information. figure 12 shows the block diagram for the mct. the mct configuration registers are described in chapter 7, ? configuration registers ? on page 123. figure 12. memory controller (mct) block diagram note: * biu data bypasses ecc generation and passes the system bus ecc directly to memory. write request agp request data request ecc merge mux* gart table walk (gtw) four read requests data acknowledge data read data gart read data memory request arbiter (mra) memory data path (mdp) mdp control next request accept request sdram memory controller (smc) ecc check address and controls sdram interface sdram accept request
64 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information mct features the mct has the following features: n support for up to three, 168-pin sdram dimms using 16-mbit (with the exception of 32-bit wide devices), 64-mbit, and 128-mbit density sdrams. n support for sdram dimms with either 72 bits with error correcting code (ecc) or 64 bits with no ecc. n support for up to 768 mbytes of memory (128-mbit by four technology equals a 256-mbyte per slot capacity for up to 768 mbytes). n support for up to four open pages within one cs (the device selected by chip select) for one-quadword agp requests. n support for ecc with no scrubbing or correction of memory. ecc from the amd athlon system bus is passed directly into memory without checking and regeneration. no support for parity generation and checking is provided. n support for only one speed of sdram. the mct does not support a different scas# latency for each socket. n power-down of the chipset is supported through the sdram automatic refresh. n automatic refresh of idle slots (attempt to keep refresh from stealing bus utilization). n the mct selects the next request to optimize bus utilization as first importance (with configuration registers to limit starvation) and then by the actual importance of the request. n the mct tracks up to four open pages and optimizes for up to four open banks within a chip select (cs). mct blocks the mct consists of the blocks described in this section. memory request arbiter (mra). the mra arbitrates and optimizes between the different memory requesters ? one agp request, one memory write queue (mwq) request, four memory read queue (mrq) requests, and one mct internal request ? from the gart table walk (gtw) address translation engine (ate). (for more information, see ? gart address translation engine (ate) ? on page 100.) the mra can select one request on each cycle and present it to the sdram memory controller (smc). sdram memory controller (smc). the smc takes each request presented from the mra and schedules and optimizes the correct events onto the sdram interface. in addition, the smc
chapter 5 functional operation 65 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information controls traffic and ecc production in the memory data path (mdp), refreshes sdram, power-down, and power-up, initializes sdram on reset, and sets the mode register inside the sdram with a bios-specified value for device 0, offset 5a, bit 7. memory data path (mdp). the mdp is responsible for providing and distributing data for memory requests and for dealing with ecc and write-merging memory write requests of less than 64-bits that require ecc. 5.3.3 address mapping and memory organization addresses are decoded into the following four controls for sdram operation: n cs (chip select) ? three dimm sockets are supported, each with up to two cs signals (cs[5:0]#). each cs[5:0]# signal is determined by performing an address less-than comparison across all the end address configuration registers (see chapter 7, ? configuration registers ? on page 123) and selecting the slot associated with the lowest slot match. n bank ? bank selects one of up to four banks within a cs (or memory module selected by cs). the bank signal is encoded in two bits that select either two or four banks within a cs. n row ? row selects one of up to 8-kbyte rows within a bank. row addresses are up to 13 bits. n col ? col selects one of up to 4-kbyte quadwords within each row. column addresses are up to 12 bits. these four parts of an address request are translated and provided by each memory requester (agp, mwq, mrq, and ate). all signals coming to the mct are encoded. using the cs, bank, and row information, the mra selects the next request for the smc to handle. the smc then schedules the correct sequence of events onto the sdram interface and merges the bank bits onto the correct row and column bits according to the memory size of the destination, configuration register settings, and sdram organization. the memory organizations listed in table 10 on page 66 for 16-mbit and 64-mbit sdram are from current sdram specs and from the jedec standard.
66 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information . table 10. sdram memory organizations sdram organization number of sdrams needed for 64-bit bus total memory module size number of bank bits /address bits number of column bits number of row bits 16 mbit 4-bit wide device two banks x 2 mbytes 16 32 mbytes 1/ma11 10 11 8-bit wide device two banks x 1 mbyte 8 16 mbytes 1/ma11 9 11 16-bit wide device two banks x 512 kbytes 4 8 mbytes 1/ma11 8 11 32-bit wide device two banks x 256 kbytes ? not supported 2 4 mbytes 1/ma10 8 10 64 mbit 4-bit wide device four banks x 4 mbytes 16 128 mbytes 2/ma12-13 10 12 two banks x 8 mbytes 16 128 mbytes 1/ma13 10 13 8-bit wide device four banks x 2 mbytes 8 64 mbytes 2/ma12-13 9 12 two banks x 4 mbytes 8 64 mbytes 1/ma13 9 13 16-bit wide device four banks x 1 mbyte 4 32 mbytes 2/ma12-13 8 12 two banks x 2mbytes 4 32 mbytes 1/ma13 8 13 32-bit wide device four banks x 512 kbytes ? not supported 2 16 mbytes 2/ma11-12 8 11 two banks x 1 mbyte ? not supported 2 16 mbytes 1/ma12 8 12 128 mbit 4-bit wide device four banks x 8 mbytes 16 256 mbytes 2/ma12-13 11 12 8-bit wide device four banks x 4 mbytes 8 128 mbytes 2//ma12-13 10 12 16-bit wide device four banks x 2 mbytes 4 64 mbytes 2//ma12-13 9 12 32-bit wide device four banks x 1 mbytes 2 32 mbytes 2/ma12-13 8 12 note: shaded rows indicated unsupported memory sizes.
chapter 5 functional operation 67 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.3.4 sdram interface memory figure 13 shows an sdram interface example. figure 13. sdram interface example memory detection the AMD-751 system controller can accommodate different memory sizes in different slots. to determine the type and size of the memory device, the bios can use the serial presence detect (spd) feature found in pc-100 dimms (using the amd-756 peripheral bus controller to read dram information) or a more general-purpose sizing algorithm. see the amd athlon ? bios developers guide , order# 21656 for more information. error correcting code (ecc) the AMD-751 system controller supports error correcting code (ecc) to check the integrity of transactions with system memory. ecc, also referred to as hamming code, corrects single-bit and some double-bit errors. the dram ecc status register is enabled in device 0, offset 59h ? 58h (see page 145). scasb# 168-pin, 64- or 72-bit sdram dimm module we2# we0# scas2# scas0# sras0# cs[5:0]# 168-pin, 64- or 72-bit sdram dimm module 168-pin, 64- or 72-bit sdram dimm module sras2# 0 1 2 3 4 5 scas1# sras1# we1# mdp[7:0] mada[14:0] dqm[7:0]# madb[14:0] md[63:0] AMD-751 ? system controller
68 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information ecc operation requires that system memory be initialized on power-up. in this procedure, the bios writes to every memory location, generating valid ecc that is stored in the dram parity bits. if this procedure is not performed, errors occur when writing data smaller than a 64-bit quadword. data from the amd athlon processor includes ecc, which is passed directly into memory ? providing protection along the whole data path. memory types (72-bit and 64-bit dimms) cannot be mixed when ecc is enabled. dram refresh the AMD-751 system controller provides dram refresh that is transparent to the rest of the system. normal and burst can be selected through device 0, offset 5ah ? 5bh (see page 145). accesses to the read and posted write buffers are allowed during a refresh period. dram self-refresh mode is entered when the system enters an s1 or s2 acpi power-down state. in addition, the AMD-751 system controller contains a refresh counter that provides 4096 refresh cycles on ma[11:0]. the refresh period is derived by dividing mcke by 512, 1024, 1536, or 2048. the refresh period is programmed in the dram mode/status register (device 0, offset 5ah) bits 1 ? 0. figure 14 shows the dram refresh timing. figure 14. dram refresh timing mcke ma[13:0] sras0# sras1# sras2# scas[7:0]#
chapter 5 functional operation 69 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information for example, in a system with sysclk = 100 mhz and a refresh interval of 1024 cycles every 16 ms, the refresh divisor is calculated as follows: refresh interval/refresh cycles refresh cycles clock period (16 x 10 C3 sec) / 1536 cycles (1536 cycles) (10 x 10 -9 sec) refresh state machine the refresh state machine keeps track of when each of cs[5:0] needs to be refreshed. each cs is refreshed independently. refresh is only performed on rows that are populated. a concurrent refresh cycle can be executed in parallel with other read and write requests, if there is no cs conflict and the command bus is free. figure 15 shows the refresh timers and counters. figure 15. refresh timer and counters refresh state machine refresh timer cycle count 14 bits smcbusycs[7:0] refcs busy refresh state machine cs_urgentref refcs, addr, cmd, v refaccept pick 1 cs cs0 refresh counter to memory request arbiter (mra) cs1 refresh counter cs2 refresh counter cs3 refresh counter cs4 refresh counter cs5 refresh counter
70 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information sdram initialization initialization can be broken down into two parts. the first is the sdram initialization and the second is the bios initialization to configure the mct for correct and optimal operation. sdrams require the following sequence to initialize: 1. bring up v dd and start the clock (done by external logic). 2. assert mcke and dqm inputs high, hold the other inputs at a nop command ? the mct forces this condition when reset# is asserted. 3. wait 100 to 200 microseconds (which is ensured by reset# staying asserted for this length of time), perform a minimum of eight auto-refresh cycles to all banks by setting the sdram initialization bit of the dram mode/status register (device 0, offset 5ah, bit 9), and set the refresh counter refresh value (offset 5ah, bits 1 ? 0) to 11 (see page 146). then wait until sdram initialization status (bit 9) is reset, which indicates that eight refresh cycles have occurred. the bios then turns off refresh again by writing a zero into the refresh. 4. write a 1 to sdram operation mode select (offset = 5ah, bit 7) to issue a mode register set command. the bios then needs to write to the address corresponding to the value to which the mode register is set (the mode command is on the address lines and default address mapping is set to 16 mbits). the conditions should be set as follows: a11 ? a7 must be equal to 00000b. a6 ? a4 = 010b for scas#=2 or 011b for scas#=3. scas# latencies of 2 or 3 are specified by dimm manufacturers (see ? synchronous dram (sdram) ? on page 72). a3 = 1 (for interleave burst). a2 ? a0 = 011b for eight quadword bursts. row a11 ? a0 corresponds to a11, a12, and a22 ? a13 in 16-mbyte address mapping. see table 23 on page 142 for address mappings.
chapter 5 functional operation 71 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information memory controller initialization to correctly initialize the mct, the bios must perform the following steps: 1. program dimm timing values in device 0, offset 54h. 2. enable the refresh counter (device 0, offset 5ah, bits 1 ? 0) with a conservative value (for example, 11 = 512 cycles between refreshes). 3. set the timing configuration registers to the worst case timing of any dimm. 4. enable each cs, one at a time, by using the bank-enable registers (device 0, offsets 40h ? 4bh) and perform the following steps to determine the size of each cs: a. configure each cs to be a 256-mbit memory module with a 512-mbyte ending address. b. write a unique pattern into the topmost quadword of memory (address = 3ff_ffffh). c. read the location (address = 3ff_ffffh). if the pattern read is the one written in the previous step, it is a 512-mbyte module. if not, then: i. write a unique pattern into the topmost quadword of memory (address = 1ff_ffffh). ii. read the location (address = 1ff_ffffh). if the pattern read is the pattern written in the previous step, it is a 256-mbyte module. if not, then: * keep changing the msb to 0 until the size is determined. d. repeat this process for each slot until the number of slots is determined. 5.3.5 shadow ram to prevent altering the content of this crucial system code, the bios normally resides in rom. because rom is substantially slower than ram, most systems provide for copying the rom contents to the upper memory area of ram and making that area read-only. the portion of ram containing the bios copy is referred to as shadow ram. the AMD-751 system controller does not contain any hardware to support the shadowing of system, video, and other bios functions to accelerate access. this capability is supported with the amd athlon processor memory type and range registers (mtrr).
72 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.3.6 synchronous dram (sdram) the AMD-751 system controller only supports synchronous dram (sdram), which is a cost-effective, mainstream type of system memory. sdrams use a clock to synchronize address and data rather than row and column strobes. the net effect is burst performance that approaches sram. in addition, sdrams can be programmed to select the burst length, write mode, and type of burst (sequential or linear). the pc-100 specification has standardized the characteristics of sdram dimms. table 11 shows the timing parameter pc-100 rev. 1.0 sdram dimm part nomenclature used by manufacturers. sdram memory does not toggle scas# to get new data, but simply increases a counter to supply the address for succeeding cycles, which substantially reduces bus delays. the basic characteristics of sdram are as follows: n sras# and scas# act as clock enables rather than strobes. n the output drivers remain on when scas# is negated. they are turned off when we[2:0]# or cs# is asserted high or when the burst count expires. n read data is valid until the next rising clock edge. n write data is sampled on each rising clock edge. n dqm[7:0]# determine which bytes are read or written. n control signals need only be valid during cs#. the bios configures the memory controller for sdram memory operation by programming device 0, offset 55h ? 54h (see page 143). table 11. pc-100 rev. 1.0 sdram dimm part nomenclature t cl t rcd t rp comments 2 clocks 2 2 lowest latency 3 clocks 2 2 3 clocks 2 3 3 clocks 3 3 highest latency notes: t cl is the scas# latency. t rcd is the sras# to scas# delay. t rp is the row precharge.
chapter 5 functional operation 73 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information multiple pages open using sdram, the AMD-751 system controller allows multiple pages in a dimm module to be open at the same time, which increases the effective memory bandwidth by eliminating some ras cycles. sdram at 100 mhz when using sdram on a 100-mhz memory bus, some special considerations and analysis are required. this section describes the 100-mhz sdram implementation method for the AMD-751 and the timing analysis required for reliable system design. an unbuffered sdram dimm organization is used for this analysis. for the 100-mhz sdram system, it is assumed that a maximum of 10 clock loads are allowed on one dimm slot (single or double rows). this constraint implies the following: n to support 4-bit wide devices, the zero delay buffer (zdb) provides up to four clocks per dimm to distribute the load. n 8-bit wide devices can be used in single-row, unbuffered dimm modules. unbuffered dimms cannot be used in the case of dual-row dimms because of 16/18 loads on sras#, scas#, and ma[11:0]. n 16-bit wide and 32-bit wide devices have no restrictions.
74 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 12 gives a more detailed sdram dimm loading analysis. table 12. sdram dimm loading analysis dimm size dimm organization sdram technology number of rows/ number of ic number of loads ma/ctrl 1 number of loads sras#/cs# 2 number of loads dqm number of loads md number of load clock unbuffered dimm modules 8 mbytes 1 mbyte x 64 1 mbit x16/16 mbit 1/4 4 4 1 1 4 8 mbytes 1 mbyte x 72 1 mbit x16/16 mbit 1/6 3 55115 16 mbytes 2 mbytes x 64 1 mbit x16/16 mbit 2/8 8 4 1 2 8 16 mbytes 2 mbytes x 72 1 mbit x16/16 mbit 2/10 4 10 5 1 2 10 16 mbytes 2 mbytes x 72 2 mbit x 8/16 mbit 1/9 9 9 1 1 9 32 mbytes 4 mbytes x 64 4 mbit x16/64 mbit 1/4 4 4 1 1 4 32 mbytes 4 mbytes x 72 4 mbit x16/64 mbit 1/6 3 66116 64 mbytes 8 mbytes x 72 8 mbit x 8/64 mbit 1/9 9 9 1 1 9 64 mbytes 8 mbytes x 64 4 mbit x16/64 mbit 2/8 8 4 1 2 8 64 mbytes 8 mbytes x 72 4 mbit x16/64 mbit 2/10 4 10 5 1 2 10 unbuffered dimm modules (difficult to support) 32 mbytes 4 mbytes x 64 2 mbit x 8/16 mbit 2/16 16 8 1 2 16 32 mbytes 4 mbytes x 72 2 mbit x 8/16 mbit 2/18 18 9 1 2 18 notes: 1. control includes sras#, scas#, or swe#. 2. row chip select. 3. in the jedec specification, 72-bit wide ecc dimms use two extra 4-bit wide devices for a single-row dimm. 4. 72-bit wide ecc dimms use four extra 4-bit wide devices for dual-row dimms. however, to reduce loading, two 8-bit wide device s are recommended.
chapter 5 functional operation 75 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information the sdram 100-mhz scheme to achieve the 100-mhz timing, a careful system timing analysis is required. figure 16 shows the AMD-751 system controller clocking scheme. figure 16. AMD-751 ? system controller clocking scheme delay analysis the most important two numbers in the clocking scheme are as follows: n how early can the command (sras#, scas#), memory address (ma), and memory data (md) be driven (in a write cycle)? n how late can the returned data be latched? figure 17 on page 76 shows the 100-mhz sdram timing in detail. table 13 on page 77 contains descriptions of the timing variables. sysclk (100 mhz) system clock generator sdram clk_in AMD-751 ? system controller sdram clk_out zero delay buffer (zdb) sdclk[11:8] sdclk[7:4] sdclk[3:0] dimm #2 dimm #1 dimm #3
76 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 17. 100-mhz sdram detailed timing tsu tsu th tsu tsu tvd tvd tprop tvd tvd tprop tprop tvd tprop tprop tcq tcq tprop tprop gr-100 0ns 50ns clock early clock late clock ma ma (delay) sras#,scas#,we# ctrl (delay) md (write) md (write delay) md (read) md (read delay)
chapter 5 functional operation 77 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information signal timing analysis. the following equation calculates how early the AMD-751 system controller needs to send out sdram address and control signals. the calculation is as follows, with the reference as the external system clock: t prop = t cycle C (t vd + t ckskew + t setup ) where: n t cycle ? 100-mhz cycle time = 10 ns n t vd ? clock to output valid delay = 6 ns n t ckskew ? total allowable clock skew and phase error between the AMD-751 and sdram = 0.325 ns n t setup ? sdram setup requirement = 2 ns n t prop ? AMD-751 to sdram propagation delay < 1.675 ns the result shows that, if the system clock is used to drive the sdram clocks, only a very short propagation delay is allowed. to allow greater propagation delays and compensate for the t vd time, use a zdb to drive the sdram clock. for more information on sdram timing analysis, see the AMD-751 ? system controller sdram cookbook, order# 22912. table 13. key sdram dimm timing variables timing variable scas#=3 scas#=2 description tcl = taa 3 2 scas# latency ? the fundamental timing number that communicates how many cycles it takes to activate or read data. tcl=4 is supported for buffered sdram. trcd 3 ? 2 2 sras# to scas# latency ? the delay from activation to rd/wr command. trc 8 ? 75 ? 7 bank cycle time ? the minimum time from activation to activation of the same bank, or auto refresh to activation (mode register set command). tras 5 3 ? 5 minimum bank active time ? the time from activation to precharge of the same bank. trp 3 2 precharge time ? the time from the precharge command to when the bank can be activated again (mode register set or refresh). trw 1 1 timing variable ? dictates r->w for how many nop cycles must exist between rd and wr and when the data bus needs to be tri-stated before the last read data. not configurable. tdimm 1 1 one cycle for dimm turn-around time for page miss. not configurable. trrd 2 2 bank to different bank in same slot delay time ? the delay from activating two banks within the same slot. not configurable.
78 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.4 pci bus controller the AMD-751 system controller drives the 32-bit pci bus synchronously with the pci clock (pclk) supplied by the system clock generator. the AMD-751 converts the 64-bit processor data to 32-bit pci data and regenerates commands with minimal overhead. a processor-to-pci post write buffer enables the processor and pci to operate concurrently. the AMD-751 converts consecutive processor addresses to burst pci cycles. a pci-to-dram post write buffer and a dram-to-pci prefetch buffer enable concurrent pci bus and processor-dram accesses during pci-initiator transactions. when the processor drives an i/o cycle to an address other than the AMD-751 system controller configuration register addresses, the AMD-751 passes the i/o cycle to the pci bus. the AMD-751 posts the i/o cycle in one of its write buffers. the AMD-751 does not respond to i/o cycles driven by pci initiators on the pci bus. the AMD-751 allows these cycles to complete on the pci bus. a memory write is the only transaction permitted from pci to agp. each pci block can be broken up into two sub-blocks ? the pci target module and the pci master module. the pci target module handles cycles initiated by an external master on the pci bus. the AMD-751 responds to cycles that are directed to main memory or writes that are sent to the other pci interface. this module contains write buffers (pci-to-memory and pci-to-pci), read buffers from memory, and a target sequencer that keeps track of the bus while the AMD-751 is a pci target. memory requests from both the pci interfaces are sent through the mro. see ? agp system dram interface (sdi) ? on page 90 for more information. the pci master module handles processor-to-pci bus cycles. within a processor stream, no reordering is done. 5.4.1 memory coherency the AMD-751 system controller determines whether the data accessed through the pci buses are coherent. data written by the processor is made available for pci reads and data from pci writes is provided to the processor when it reads the same
chapter 5 functional operation 79 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information location. if the pci cycles get mapped through the gart, the AMD-751 performs one of the following actions to guarantee coherency: n if this memory is cacheable, the processor should only access this memory through its physical address space and not through the gart. the pci bus can access the memory either through the gart table address space or through the standard physical address space. n if the processor cannot guarantee accesses to this space through the physical address space, it needs to use the same data type as in agp (write-combining and noncacheable). note: for more information about the gart, see ? gart cache operation ? on page 98. 5.4.2 pci arbitration the AMD-751 system controller contains arbitration logic that allocates ownership of the pci bus among itself, the amd-756 peripheral bus controller, and five other pci initiators. when there are no requests for the bus, ownership defaults to the processor through the AMD-751. parking the bus in this manner is sometimes referred to as processor-centric arbitration. the AMD-751 can be programmed to be memory-centric, which parks the bus on the pci master. this mode is controlled by device 0, offset 84h, bit 0 (see page 154). 5.4.3 pci configuration the AMD-751 uses pci configuration mechanism #1 to select all of the options available for interaction with the processor, dram, and the pci bus. this mechanism is defined in the pci local bus specification revision 2.2 . all configuration functions for the AMD-751 are performed by using two i/o-mapped configuration registers ? io_cntrl (i/o address 0cf8h) and io_data (i/o address 0cfch). these two registers are used to access all the other internal configuration registers of the AMD-751. the AMD-751 decodes accesses to these two i/o addresses and handles them internally. a read to a nonexistent configuration register returns a value of ffh. accesses to all other i/o addresses are forwarded to the pci bus as regular i/o cycles. read and write cycles involving the AMD-751 configuration registers are only distinguished by the address and command that is sent.
80 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.4.4 pci southbridge signals the AMD-751 supports one pair of pci request/grant signals, preq# and pgnt#, to connect to a southbridge device such as an isa/eisa bridge. these signals are generally used when a pci device, an isa master, or a dma device requires ownership of the system main memory. the isa bus device asserts preq# to request the bus. the AMD-751 system controller grants the request after all of its write buffers have been flushed by asserting pgnt#. note: the AMD-751 system controller allows a southbridge device to hold preq# for an extended time in order to complete an isa transfer and avoid a potential deadlock condition. 5.4.5 pci parity/ecc errors the AMD-751 system controller indicates that an ecc error occurred on the memory bus by setting bit 15 in the status register (device 0, offset 07h ? 06h). on the pci bus the AMD-751 does not check parity on the pci bus. the status bit (device 0, offset 07h ? 06h, bit 8) is always zero. 5.4.6 pci-to-memory/pci-from-memory and other pci targets the pci target memory write fifo is used to gather pci writes-to-memory into cache lines. only writes from a single pci write transaction are gathered. by gathering them into complete cache lines, the probe (snoop) to the processor can invalidate the cache line instead of writing it back to the memory. in the case of a partial cache line write, the data is always written back to memory. a dedicated pci fifo is used for writes going to the other a-pci interface. in addition, this fifo allows the pci master to burst, gathering 32 bytes at a time, which improves performance. the pci target read fifo is used to hold the cache line being read from memory. in addition, it is used to merge writeback data from the processor cache. the size of this fifo is large enough to allow read prefetching.
chapter 5 functional operation 81 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.4.7 pci-to-processor bus read transactions the AMD-751 contains an 8-byte read buffer that assembles two 32-bit pci read cycles into one 64-bit quadword for the processor data bus. in addition, the buffers are used when any read crosses a 32-bit boundary. aligned byte/word/doubleword processor reads are passed on to the pci bus by the AMD-751 system controller. the read buffer is always enabled. when the processor reads from the pci bus, the AMD-751 acts as a pci initiator. the AMD-751 responds to the read with data from one of its internal buffers, or with data obtained by performing a read operation on the pci bus. 5.4.8 processor-to-pci bus write transactions the AMD-751 system controller converts a full 64-bit (quadword) processor-to-pci write into two consecutive 32-bit (doubleword) pci write cycles. this feature reduces the bus bandwidth required to complete pci writes. the AMD-751 contains a post-write buffer between the processor and the pci bus. every processor-to-pci write is stored in the buffer unless it is full, allowing the processor to begin its next operation without having to wait for the write to complete. when the pci bus is available, the AMD-751 performs up to five 32-bit pci writes to complete the transaction. processor to/from the pci buses (pci master) the pci master write fifo is used to store the data for a processor-to-pci write, which allows concurrent writes to both pci buses. the architecture support is optimized for 64-byte transfers. in addition, this fifo can hold multiple smaller transfers. in the case of video capture cards sitting on the standard pci bus, pci-to-agp pci write cycles are also sent through this buffer. the pci master read fifo is able to hold the largest processor read from the secondary pci bus. the standard pci bus is optimized for single quadword accesses. burst cycles the AMD-751 writes all of its buffer contents in a single pci transaction when the bus becomes available. in this way, consecutive processor-to-pci writes, whether two full quadwords or several smaller transactions combined through byte merging, are performed in a single pci transaction.
82 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.4.9 pci accesses by an initiator a pci initiator begins a memory read or write cycle by asserting frame# and placing the memory address on ad[31:0]. the AMD-751 system controller decodes the address. if the address is within the domain of the processor or memory, the AMD-751 accepts the cycle and responds as a pci target by asserting devsel#. if the address is not within the AMD-751 or processor domain, the AMD-751 ignores the cycle and allows it to complete on the pci. prefetch options read requests from the pci block to the mro are made in terms of cache lines only. after fetching the initial cache line, it is possible to start prefetching the next cache line. prefetching the next cache line is preferred, because the pci master typically reads more than one line, but can waste dram bandwidth if this line is thrown away. read/write request the length of a read request is always eight quadwords (one cache line). during writes, the AMD-751 attempts to accumulate an entire cache line. if the start address is not cache aligned, the AMD-751 makes single write requests until it gets cache aligned. when aligned, it makes a request every eight quadwords. each time a write request is made, the request length is reset. if a partial quadword write is detected, no more data is accumulated and a request is issued. when there are a few accumulated quadwords and then there is a partial quadword write, the request is broken up into two requests ? one request with the current length minus 1 containing all enabled bytes, and one request of a single partial-quadword write. this splitting up of requests is done in the pci sdi request queue. request queue when the queue is empty, the request passes through and is sent directly to the sdi and the other pci bus. if the sdi is not ready to accept the request or there is a gart translation involved, the request is held in the queue.
chapter 5 functional operation 83 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information write data and byte enables the pci data bus is 32 bits wide while main memory and internal data buses within the AMD-751 are 64 bits wide. when a pci write occurs to memory (and the other pci interface), two consecutive doublewords are accumulated into a quadword of data. in addition, the corresponding byte enables are accumulated. data and byte enables corresponding to the lower doubleword are latched. when the high doubleword is written, this data along with the latched lower doubleword are written to the write data fifo. when there is no write to the upper doubleword, the corresponding byte enables must be inactive while writing the latched lower doubleword to the write data fifo. if the first write is to the upper doubleword, the lower byte enables must be masked off. 5.5 accelerated graphics port (agp) the accelerated graphics port (agp) is a point-to-point connection between a graphics adapter (agp initiator) and a memory controller (agp target) that enables the adapter to store and use graphics data in main memory. this connection relieves graphics traffic from the pci bus and greatly accelerates video performance. the AMD-751 system controller functions as an agp target, providing all the signals, buffers, and logic required for full compliance with agp specification version 1.0. agp features while agp relieves traffic on the pci bus and frees up graphics adapter memory, the greatest impact on system performance comes from the many innovations agp brings to data transfer operations. these improvements include the following: n split transactions ? requests to read or write data are separate from the data transfers. n pipelined requests ? requests can be issued contiguously and stored in the AMD-751 system controller request queue. pipelining allows agp to achieve high levels of concurrency with pci and the processor. n pipeline grants ? pipelined gnt# signals for up to four write transactions.
84 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information n prioritizing (reordering) ? read and write requests can be assigned a high priority or a low priority to ensure that more urgent requests are serviced first. n a command set geared toward optimizing queued, prioritized requests. n defined-length requests ? the amount of data requested is indicated in the agp command, rather than the duration of an asserted signal, such as frame# in pci. n an 8-byte minimum data size for agp 2x transfers, which provides a more efficient method for moving the large amount of data typical in a graphics request. n a separate, optional sideband address (sba) bus that enables concurrent transmissions of requests and data transfers. n an optional 2x mode that doubles the agp graphics adapter data transfer rate (double-pumped transfers at 66 mhz). n freedom from the coherency requirements of pci, which eliminates the latency resulting from cache snooping. n full pci 2.2 capability, which enables the AMD-751 to pass programming information from the processor to the graphics adapter. n a deep request queue. n a graphics address remapping table (gart). see ? gart cache operation ? on page 98 for more information.
chapter 5 functional operation 85 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.5.1 agp block diagram figure 18 shows the agp block diagram. figure 18. agp block diagram gart cache the gart cache is made up of the gart directory caches (gdc) and the gart table cache (gtc). the request is read out of the queue in the address module, and the virtual address is translated into a physical address. if the corresponding gart entry is not present, a request is sent to the ate, a gart table walk is performed, and the entry is fetched from the memory. wrq rdq wbt sdi axq write read seq sba arbiter dram request agp write data agp read data dram write data dram read data addr ad recv sba recv ad xmit seq agp i/o agp queues agp data fifos agp bus agp bus memor y controller gart agp address fifo fifo and rof legend : ad xmit ad bus transmitter sba sideband address axq agp transaction queue sdi system dram interface rdq read request queue seq sequencer recv receive wbt write buffer tag rof reorder fifo wrq write request queue tlb miss
86 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information see ? gart address translation engine (ate) ? on page 100 for more information. 5.5.2 the agp queues this section describes the queuing structures in the AMD-751 system controller agp block. there are two types of queues ? request queues and transaction queue. when an agp request is detected, either in the standard pipe# mode or through the sba mode, it is written to the request queues. these queues sort the request based on priority and present the next request to be serviced (based on priority). there are two queues ? one for reads and one for writes, each with a depth of eight entries. because the output of these two request queues goes to different blocks, they can both send out requests at the same time. the AMD-751 queues and data buffers streamline agp read and write requests and data transfers. these queues and buffers are shown in figure 19 on page 87.
chapter 5 functional operation 87 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 19. agp queues and buffers agp request queue the agp request queue has the following specifications: n two queues ? one for read requests and one for write requests. n 40 bits per entry in each of the request queues. n holds the gart-translated physical address. n each queue automatically reorders high-priority requests in front of low-priority requests. n the write request queue (wrq) interfaces to the write buffer tag (wbt) and the agp transaction queue (axq). n the read request queue (rdq) interfaces to the sdi and the read acknowledge queue (rxa). n requests can be issued from both the write queue and read queue in the same clock. dram controller agp interface agp write data fifo agp read request queue agp read data fifo processor pci fifos transaction queue and gart table walk agp write request queue agp bus reorder fifo gart tlb graphics adapter
88 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information structure of the agp request queue the agp request queue is split up into two queues ? one for read requests and one for write requests. because there is a reordering fifo in the address module, the request queues do not have to be large. the read queue is big enough to hold all outstanding read requests, which avoids stalling writes that run on the bus while the reads are being done on memory. requests from the sba bus are multiplexed with pipe# requests and written to the same queues. high-priority requests are inserted in front of low-priority requests so that the request to be serviced is at the top of the queue. this reordering is done dynamically as a new request is written into the queue. because requests from each of the queues go to a different sub-block, requests can be read out of both the queues at the same time. the dram starts fetching data from memory and the write data is sent across the agp bus at the same time. read ordering with respect to writes the agp ordering rules specify that writes are ordered ahead of reads. reads are serviced only when all the preceding writes have been written to memory, which is only required for low-priority requests and does not affect high-priority read requests. when a low-priority request is the next one to be serviced from the read queue, the tag of that request is sent to the write queue module and wbt modules. the tag is compared with all valid entries in the two modules. if any of them hits (matches), the read request is blocked. after the write requests get serviced, the read is allowed to proceed. agp request queue. in general, the agp request queue services agp requests in the order received, subject to their priority (read high, write high, read, write). ordering rules. the request queue is subject to the following agp ordering rules: n read requests are processed in the order they are received. n write requests are processed in the order they are received. n reads push writes, meaning that a write request is serviced before a subsequently received read request is serviced. n writes can pass reads, meaning that a write request can be serviced before a previously received read request. n there are no ordering restrictions between agp and pci transactions on the agp bus.
chapter 5 functional operation 89 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information n pci transactions on the agp bus follow the pci ordering rules described in the pci local bus specification, revision 2.2. n high-priority reads and writes bypass low-priority reads and writes. if a low-priority data transfer is in progress when a high-priority request is received, the data transfer completes before the high-priority request is serviced ? that is, a request is not preemptable. a high-priority request supersedes a low-priority request on a request boundary only. the AMD-751 system controller ignores the processor lock# signal when the graphics adapter reads a location in memory that is currently locked by the processor. in addition, the agp pci bus does not honor lock# from the primary pci bus. if a pci master attempts to access a locked location, the access proceeds normally and generates a retry (or an serr#). using lock# can result in a system hang or other operational problems. lock# is not normally used on the pci bus and its use should be avoided. in addition, because agp does not enforce coherency, read requests can return stale data and write requests can be overwritten by cached data when it is written back. agp provides two commands, flush and fence, to give software control over request ordering. fence command the fence command ensures that all requests preceding it are processed before all requests that follow it. write requests issued after the fence command do not pass read requests issued before the fence command. flush command the flush command forces the immediate servicing of all write requests in the request queue. a single quadword of random data is returned when the last write is completed. this process forces all data residing in the AMD-751 system controller buffers to be visible to the rest of the system, ensuring that a subsequent memory access returns the correct agp data. after the flush request gets queued, and until it is serviced, any high-priority write requests entering the queue are serviced before the flush occurs.
90 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information agp transaction queue the agp transaction queue (responses to agp requests) holds information about transactions that are ready to run on the agp bus. write transactions are put into this queue as soon as the request is retired from the request queue. read transactions only enter this queue after some data for that transaction is available in the read buffer. the arbiter looks at this queue to decide which transaction should be granted the bus next. in addition, the bus sequencer looks at this queue to know what transaction to run next. the order in which the transactions are sent to the queue is the order in which the transactions are run on the bus. 5.5.3 agp system dram interface (sdi) the agp logic interfaces with the mct through the system dram interface (sdi). the sdi gets write requests from the write buffer and read requests from the read request queue. it arbitrates between these two requests and sends the request on to the mct. in addition, it is responsible for breaking requests down to the size that the mct can accept and making sure that requests do not cross a dram page boundary. the sdi has a two-level pipeline so that, if there are a number of small requests pending, it can continuously accept these requests and send them on to the mct on every clock. memory request address and length calculation in an x86 system, the memory burst sequence is interleaved and the agp burst sequence is linear. therefore, bursts can be done only when they are aligned to a cache-line boundary. the maximum size of a request to the memory controller is eight quadwords. the sdi sub-block checks that the address is cache-line (or four quadword) aligned. if it is not aligned, the AMD-751 system controller requests single quadwords. otherwise, the AMD-751 requests an entire block (eight quadwords). in addition, in the case of writes, if all the bytes in the transaction are not enabled and if ecc is enabled, the transaction is broken down into single quadword transfers.
chapter 5 functional operation 91 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.5.4 agp arbitration the agp arbiter is responsible for granting the bus to the master in response to a bus request, and for scheduling data transactions that are ready to run on the agp bus. in addition, the agp arbiter can generate pipelined data grants to get the maximum bandwidth. there are three different arbiters in the AMD-751 system controller ? the pci arbiter, the memory arbiter, and the agp arbiter. the relationship between these three arbiters and their various inputs is shown in figure 20. figure 20. AMD-751 ? system controller arbiters req0 req1 req2 req3 req4 agp data req. processor_agp_req agp master rq transaction priority tag agp-req read high write high read write pci-mem-req pci arbiter request queue dram agp bus arbiter queue graphics adapter pci bus ctrl a_gnt# processor_pci_req pci_bus_grants processor steering request processor sba bus a_ad bus memory arbiter processor_mem_req pci/a-pci arbiter priority high/low a-pci_mem_req agp rd/wr agp data l/h amd-756 ? peripheral bus controller
92 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information pci arbiter the pci arbiter receives requests from the processor, the amd-756 peripheral bus controller, and other pci agents, and determines which request is serviced on the pci bus. memory arbiter the memory arbiter receives requests from the processor, the pci arbiter, and the agp request queue. requests are serviced on a first-come, first-serve basis. agp bus arbiter the agp bus arbiter prioritizes requests for the agp bus in the following order: 1. high-priority data 2. agp accesses from the processor 3. pci requests from the graphics controller 4. low-priority data high-priority agp requests are serviced before any other agp bus requests. the processor is second in the priority chain, ensuring that it is not locked out by other requests. however, processor traffic to the frame buffer can constitute a significant portion of the traffic on the agp bus. back-to-back processor requests with a tight polling loop could starve out the ability of the graphics controller to queue new transactions and prevent the transfer of low-priority agp data. to avoid this situation, systems employing polling loops rather than interrupts should pad the loops with delays. graphics controller (agp master) address requests and pci cycles are third on the agp bus priority chain. these requests have priority over low-priority agp data transfers, guaranteeing that the new transactions are queued using brief bus cycles by asserting pipe#. this prioritization allows the request pipeline to stay full. low-priority agp data transfers have the lowest agp bus priority so that transactions, such as a series of long reads, do not starve processor accesses to the frame buffer or the agp request pipeline.
chapter 5 functional operation 93 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5.5.5 agp data the minimum granularity of agp data transfers is eight bytes, and data is always aligned on 8-byte boundaries. smaller transfers must be done through pci cycles. agp cycles incur substantially less processor overhead than pci cycles because the caches are not snooped. however, data coherency is lost. data transfers requiring coherency should be transferred with pci cycles. to service an agp read request, the AMD-751 system controller reads the requested data from memory, stores it in its 64-quadword read data fifo, and sends it to the adapter during agp data phases. to service an agp write request, the controller accepts data from the adapter during agp data phases and stores it in its 16-quadword write data fifo until it can write the data to memory. 5.5.6 pci transactions on the agp bus using the secondary pci bus ? that is, performing pci transactions on the agp bus ? is preferable or necessary in some circumstances. to program control information into the graphics adapter, the AMD-751 system controller configures the pci registers of the adapter through the secondary pci bus. if the adapter must perform a memory read smaller than eight bytes (the minimum agp data size), it can do so by using a pci transaction. pci transactions are required in cases where data coherency must be maintained, because agp cycles do not generate cache snoops. a secondary pci transaction is indicated by the assertion of a_frame#. the AMD-751 system controller maintains a separate buffer for pci transactions that use the agp bus. the adapter can write to a pci device but cannot read from one. the AMD-751 supports pci-to-agp writes and agp-to-pci writes but does not support agp-to-pci reads or pci-to-agp reads.
94 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.5.7 graphics adapters and main memory to work with data stored in main memory, a graphics adapter must either load the data into its local memory or manipulate the data in place in main memory. the agp specification refers to these two approaches as dma mode and execute mode , respectively. while the AMD-751 system controller can implement either approach, the execute mode more effectively reduces the burden on graphics adapter memory, which is a primary objective of agp. 5.5.8 agp virtual address space (aperture) range and size the gart aperture defines the amount of memory allocated to the agp virtual address space. there are seven different agp aperture sizes available ? 32 mbyte, 64 mbyte, 128 mbyte, 256 mbyte, 512 mbyte, 1 gbyte, and 2 gbyte. depending on the selected agp aperture size, address bit 31 to bit nn (where nn is a variable bit number) of the issued agp virtual address is used for a gart range check. address bits nn ? 1 to 12 are used for translating the virtual address to a physical address. a graphics adapter requires a contiguous view of memory, but most systems allocate memory in non-contiguous blocks. to accommodate this disparity, the AMD-751 system controller implements a graphics adapter remapping table (gart) described in the agp interface specification, revision 2.0. the gart translates the contiguous addresses used by the adapter (referred to as virtual addresses) to their actual, generally not contiguous, physical addresses in main memory. the gart acts much like the page table in the processor, mapping linear addresses to physical addresses. figure 21 shows this remapping. figure 21. address remapping graphics device processor memory processor table page gart processor agp linear address physical address agp device address physical address
chapter 5 functional operation 95 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information the gart table or tables reside in memory. they are set up and maintained by device driver calls through application programming interface (api) routines as defined in the agp specification. each entry in the table(s) correlates a virtual address with a physical address. configuration registers in the AMD-751 system controller determine the location of the table(s) in memory, and the location and size of the agp memory block to which the gart translates its addresses. conventional (two-level) gart scheme the gart scheme is a conventional two-level scheme. the scheme is designed to accommodate the 4-kbyte pages employed by many systems, and requires two memory accesses to translate the agp virtual memory address to the actual physical memory address. the size of a table is constrained to one page (4 kbytes). each entry address is four bytes, limiting the table to a maximum of 1-kbyte entries. to enable the use of more than 1-kbyte entries, the conventional scheme employs multiple 1-kbyte-entry gart tables, each containing 1024 virtual address/physical address translations. each gart table entry is four bytes in length. bits 31 ? 12 are the base address of a 4-kbyte page in system memory. bits 11 ? 2 are reserved for future use. bit 1 is always ignored, and bit 0 is the valid bit. the gart table base address is aligned on a 64-kbyte boundary initialized by the device driver in the gart base address register. the memory location of each gart table is tracked in a separate, 1-kbyte-entry gart directory. therefore, there can be up to 1024 gart tables. in addition, each gart directory entry is four bytes in length, with bits 31 ? 12 containing the corresponding gart table base address. bits 11 ? 2 are reserved for future use, bit 1 is ignored, and bit 0 is the valid bit for the entry. the base addresses of the gart directory and gart tables are all 64-kbyte aligned. the AMD-751 system controller contains the following two on-board translation lookaside buffers (tlb), which reduce the number of memory accesses to the gart: n an 8-entry fully associative gart directory cache (gdc). n three fully associative gart table caches (gtc).
96 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 22 and figure 23 show the gdc and gtc hierarchy. see ? gart cache operation ? on page 98 for more information. figure 22. cache hierarchy (conventional two-level scheme) figure 23. conventional gart scheme ? multiple tables 16-entry agp gtc 8-entry processor gtc 4-entry pci/a-pci gtc 8-entry gdc master a[21:12] physical page address a[11:3] table page translation table a[31:12] a[31:22] virtual address a[31:12] physical address of virtual address final physical address virtual address supplies final physical address gart table cached in gdc cached in gtc
chapter 5 functional operation 97 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information when an address issued by the graphics controller (the virtual address) falls within agp memory range and misses both of the gart caches, two memory accesses take place. the first access uses agp virtual address a[31:22], concatenated with the page directory base, to select an entry from the gart directory. this entry contains the 20-bit base address a[31:12] of the gart page table to be used. the second memory access uses agp virtual address a[21:12] to select an entry in the gart table. this entry contains the final physical page address (ppa). figure 24 shows the two memory accesses. figure 24. page translation structures page directory base register 31 12 physical memory increasing memory address page directory table . . . 4 kbytes n (1 to 1-kbyte) entries page table pde page table entries 1-kbyte entries page table cached in gdc cached in gtc 4 kbytes base addresses note: page table entries (pte) contain the page base addresses or the page frame address note: page directory entries (pde) contain the page table base addresses.
98 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information gart table cache (gtc) the gart table cache (gtc) consists of the actual cache that stores the physical addresses corresponding to the most recently accessed virtual addresses and associated state machine. the gtcs are distributed amongst all the agents that require gart translation. therefore, there are three gtcs in the AMD-751 system controller. gart table walk the gart table walk (gtw) consists of the table walk state machine, a centralized resource that also contains the gart directory cache common to all gtcs. see ? gart address translation engine (ate) ? on page 100 for more information. gtc front end the gtc front end consists of agent-specific hooks required for optimizing normal operation (for example, agp-required page crossover detection on accesses performed before the request enters the agp request queue). 5.5.9 gart cache operation table 14 summarizes gart terminology used in this section. the AMD-751 system controller contains three gart table caches (gtcs) and an 8-entry gdc. in the two-level scheme, a virtual address that hits the gtc cache can be translated to its physical address without any memory accesses. missing the gtc, but hitting the gdc cache requires only one memory access. missing both caches requires two memory accesses. the gtc and gdc are hardware-driven and transparent to the system software except during initialization or modification by chipset device-driver management software. configuration space register bits are used to enable, disable, flush, and purge table 14. summary of gart terms term abbreviation location cached in: translation page directory table pdt memory gdc 1st level page directory entry pde memory/gdc gdc 1st level gart directory cache gdc AMD-751 1st level gart front end gfe page tables pt memory gtc 2nd level page tables entry pte memory/gtc gtc 2nd level gart table cache gtc AMD-751 2nd level
chapter 5 functional operation 99 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information gtc and gdc entries. see device 0, offsets ach ? b3h and memory mapped registers at bar1 + offset 00h to 13h. figure 25 shows the structure of page table entries. the bits in figure 25 have the following definitions: n bit 0 ? present bit 1=present and valid 0=not present/page not valid n bits 4 ? 1 reserved for future use n bits 7 ? 5 ? tlb lookup mask bits m[2:0]. a 1 in any bit position masks that bit from being compared during lookup. see table 15 for the proper use of the mask bits. n bits 11 ? 8 ? reserved for future use n bits 31 ? 12 ? 4-kbyte page base address the page cacheable bit indicates the cacheability of the page in the processor caches. if the page is cacheable, any agp/pci access to a virtual address that translates to the physical address of this page, and whose pc bit is set, must snoop the processor cache with this physical address. the pc bit is set in the page table/page directory entry in the gart by the miniport driver when 4-kbyte pages are reserved by the graphics application. for texture data, the page is usually uncacheable. for geometry data, it is advantageous for the page to be cacheable. 31. . . . . . . . . . . . . . . 1211109876543210 page base address rrrrm2m1m0rrrrp figure 25. page directory entry (pde) definition table 15. mask bits number of pages m2 m1 m0 1 000 2 001 4 011 8 111
100 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information distributed gart ? gdc features the gart directory cache (gdc) contains three gart table caches (gtc) ? one each for the processor, agp, and pci/a-pci. these gtcs have the following features: n the agp gtc is a 16-entry, fully associative cache. n the processor gtc is an 8-entry, fully associative cache. n the gtc for pci/a-pci is a 4-entry, fully associative cache. gart table cache (gtc) the agp gtc is a 16-entry, fully associative cache for storing the most recently used page address translation information. the implementation for the gtc returns a physical address for a gtc hit in one clock. the gtcs are distributed tlbs. the entire tlb array is used for each agent that requires gart translation, which minimizes table walks for accesses from each agent. the gtc sizes in each agent are different. gart address translation engine (ate) the gart address translation engine (ate) is a state machine responsible for the entire address remapping process, which includes the following functions: n routing the agp virtual address to the gtc and/or gdc n conducting cache searches n initiating a memory request for a gart directory or gart table entry after a cache miss n deriving the physical address either from cache or memory n routing the physical address to the dram controller gart table walk (gtw). the gart table walk is part of the ate state machine that handles the table walk functions for gtc misses from each of the gtcs, and fetches the translated physical address top-of-page from the table entries in memory. figure 26 on page 101 shows the address translation flow.
chapter 5 functional operation 101 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 26. address translation flow chart table 2 (gtc) search table #1 memory access table #2 memory access physical page address a31 ? a12 virtual page address a31 ? a12 miss in gart range? yes bypass (no translation) no hit table #1 (gdc) cache search miss hit two-level indexing? yes no request to gtw physical address = virtual address gtw
102 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information page directory entry (pde) each pde is 32-bits wide. bits 31 ? 12 form bits pa[31:12] of the physical address (pa) used to fetch the pde. bits 11 ? 2 are formed by bits 31 ? 22 of the linear address provided by the graphics master. bits 11 ? 8 of the pde are reserved for future use, bits 7 ? 5 are mask bits (see table 15 on page 99), and bits 4 ? 1 are reserved. bit 0 indicates a valid entry. bits 31 ? 12 of the pde concatenated with bits 21 ? 12 of the linear address form the 32-bit page table address from which the page base address is fetched from memory. note: bits 21 ? 12 of the linear address represents bits 11 ? 2 of the page table address (or the page table offset). bits 31 ? 12 of the page base address, concatenated with bits 11 ? 3 of the linear address (that is, the page offset) forms the physical address in memory from which the operand is finally fetched. figure 27 on page 103 and figure 28 on page 104 show this translation scheme. the page directory table (pdt) contains up to 1-kbyte entries, depending on the amount of remapped graphics memory.
chapter 5 functional operation 103 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 27. two-level gart translation scheme 12 11 0 page directory 22 21 page table offset page offset offset 31 0 page directory base 2 page directory offset fetch from memory 31 12 11 (from linear address) 12 11 0 page table base 2 page table offset fetch from memory (from linear address) 31 31 12 11 0 page offset (from linear address) fetch operand from memory page base
104 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 28. another view of the two-level indexing scheme gtc data the gtc supports the referencing of a variable number of pages by one gtc entry. the gtc allows for some virtual address bits to be selectively masked, depending on the number of contiguous pages, before a comparison is done with the stored virtual address. up to eight contiguous pages aligned on an eight-page boundary can be combined. the number of contiguous pages that one gtc entry can be referenced in the gtc (with the appropriate mask bits ? see table 15 on page 99) is equal to the actual number of contiguous pages approximated to the nearest lower power of 2. therefore, if there are seven contiguous pages starting on an 8-page aligned boundary, the following conditions apply: n the first gtc entry references four physical pages. n the second gtc entry references two physical pages. n the third gtc entry references one page. physical memory gart directory directory entry 2 1-kbyte table entries 1-kbyte table entries gart table directory cache table cache gart base address register points here (device 0, bar1 + 04) AMD-751 ? system controller (northbridge) (up to 1-kbyte directory entry 1 entries)
chapter 5 functional operation 105 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information in the scheme where ptes and pdes reference a variable number of pages, each pte refers to a variable number of pages, depending on the number of contiguous pages starting from the page whose physical address is given by bits 31 ? 12 of this pte. the gtc uses this pte to increase its hit rate. because the chipset miniport driver sets up the ptes and programs the page directory of the chipset or table base address, it knows the number of contiguous pages equal to the nearest lower power of 2, starting from each page referenced by a given pte. software uses this number of contiguous pages to arrive at mask bits for up to three virtual address bits (14 ? 12). these mask bits are used during virtual address comparison to mask off some or all of bits 14 ? 12 before comparison, depending on the number of contiguous pages starting at this page. table 15 on page 99 explains the mask bit derivation. values other than those shown in the table are illegal. in addition, software must ensure that the first page of a contiguous block of n pages (n=2, 4, 8) is aligned on an n-page boundary. gart table cache (gtc). the gtc is a fully-associative tlb with sixteen 19-bit comparators that uses tag-comparison and a least-recently used (lru) replacement algorithm. each entry consists of one valid bit, an 18-bit vpa, and a 20-bit ppa. when a new vpa is available, it is compared with all 16 tag entries in parallel. if one of the 16 parallel address comparators matches and is qualified by the entry valid bit, the corresponding hit[15:0] signal selects the correct ppa through the output multiplexer.
10 6 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.6 power management the AMD-751 system controller supports the advanced configuration power interface (acpi) specification, on-now, and pc 98 requirements through a handshake mechanism with the processor. the counters required for these features are contained in the amd-756 peripheral bus controller companion device. smm memory remapping is handled by a model-specific register in the amd athlon processor. see the amd athlon ? bios developers guide , order# 21656 for more information about the smm remapping operation. figure 29. power management signal connections as shown in figure 29, the processor and the AMD-751 system controller communicate power state transitions through the amd athlon system bus connect/disconnect protocol and special cycles (masked writes to a defined amd athlon system cpustop pcistop 100-mhz system clocks 66-mhz agp clock 33-mhz pci clocks clock generator amd athlon ? processor AMD-751 ? system controller (northbridge) amd-756 ? peripheral bus controller (southbridge) sdrams stpclk amd athlon system bus pci cke
chapter 5 functional operation 107 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bus address with specific data encoding). in general, the processor initiates a request for a disconnect with a special cycle and the AMD-751 system controller may or may not actually disconnect the processor with the connect/disconnect protocol. the AMD-751 performs the requested connect/disconnect as part of the process of entering and exiting certain acpi states. the following two special cycles are of interest: n halt ? generated by the amd athlon processor in response to executing a halt instruction. optionally, the AMD-751 system controller (through a configuration register bit) initiates an amd athlon system bus disconnect to the processor and then sends a halt special cycle on the pci bus. in addition, when a halt-disconnect occurs, the AMD-751 places the sdrams into self-refresh operation. n stop grant ? generated by the amd athlon processor in response to assertion of stpclk#. when the AMD-751 system controller receives a stop grant from the processor, it initiates the following sequence of actions: 1. the AMD-751 system controller disables pci/agp arbitration and waits for all queues to memory to be empty (including refresh requests) 2. the AMD-751 completes the amd athlon system bus cycle. the AMD-751 then initiates a amd athlon system bus disconnect to the processor. 3. the AMD-751 sends a stop grant special cycle on the pci bus. 4. the amd-756 peripheral bus controller receives and enters the appropriate power state. the amd-756 may then assert dcstop#. note: the AMD-751 does not support dcstop#. halt special cycles are generally considered part of an acpi state definition (c1). stpclk#, however may be asserted at random times while the processor is in the full-running state (c0), which conserves power (clock throttling). the only programmable power management function in the AMD-751 system controller is bit 0 in pm2 (bar2, offset 0). this bit disables arbitration when the system is powered down.
10 8 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information acpi when the processor samples stpclk# asserted, it generates a stop grant special cycle. the AMD-751 passes this cycle to the pci bus in the form of a special cycle and preserves the address during the address phase of the cycle, although the pci specification does not require it. the the pci stop grant special cycle informs the amd-756 peripheral bus controller acpi logic to transition to the lower-power state. acpi power states the AMD-751 system controller implements two basic power states ? full-on and halt/stop grant. these states are entered and exited through special cycles from the processor. figure 30 on page 109 shows the AMD-751 power management state machine (pmsm). the two basic power states are described in this section. full-on (c0). in this state the AMD-751 system controller is fully operational, all clock trees are running, and the AMD-751 provides refresh to the sdrams. halt (c1), stop grant (c2), and sleep (c3). if the AMD-751 system controller detects a halt special cycle from the processor, the halt state (c1) is entered and the AMD-751 disconnects the processor. pci and agp masters continue to run (arb_dis clear). if the AMD-751 detects a pci dma master transaction that needs a snoop, the processor is connected and the probe cycle(s) run (c2). if the processor does not start any non-nop amd athlon system bus cycles while the probe is in progress, the AMD-751 system controller puts the processor back to sleep (c3) following the completion of the probe. if the processor starts sending non-nop amd athlon system bus cycles while connected, the AMD-751 transitions to the full-on state. if the AMD-751 system controller has detected a stop grant special cycle from the processor, the stop grant state is entered and the AMD-751 disconnects the processor. sdram is put in self-refresh mode. if software sets arb_dis, no dma activity is allowed on the pci bus and the system is in the sleep state (c3). when the AMD-751 system controller detects that the processor wishes to wake up (procrdy assertion), sdrams are taken out of self-refresh mode and the processor is reconnected.
chapter 5 functional operation 109 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 30. acpi power states running arb_dis c-bit enter pci halt/ wait disconnect flush wait for idle halt or stop grant idle disconnect abort disconnect halt and disconnect done halt and disconnect done self-refresh wait for self-refresh entered entered arb_enable trdy request from pci/agp procrdy from processor exit self-refresh exit self-refresh wait for self-refresh exit wait for self-refresh exit exited exited connect done wait connect done running any pci/agp request connect done disconnect abort no pci requests c1 if halt c3 if stop grant c2 c0 stop grant disconnect abort self-refresh self-refresh pending
110 functional operation chapter 5 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 5.7 phase locked loop (pll) features the phase locked loop (pll) has the following specifications: n peripheral clock (pclk) operates at 66 mhz. n agp 2x clock (agp2xclk) operates at 133 mhz. n core clock (cclk) can be switched between 100 mhz and 66 mhz, as defined by an input pin at reset. the core clock must be an integral multiple of 33 mhz. n the two clocks (pclk and cclk) must have a common edge. pll clock outputs the pll has two output clocks that are distributed throughout the AMD-751. the peripheral clock, which runs at 66 mhz, is used by all the sequencers and logic controlling the peripheral buses (pci and agp). the standard pci logic runs internally at 66 mhz. the external bus operates at half that speed, and the conversion is done with clock-enable logic at the bus interface. in addition, the agp logic gets the 133-mhz clock it needs for the double-pumped logic. every rising edge of the agp 2x clock has to align with an edge of the peripheral clock (66 mhz). the core clock is distributed throughout the AMD-751. it runs either at 100 mhz or 66 mhz, depending on the system board and external configuration. the pin that defines which of these frequencies to use is static and must not change during operation. the pll enables the two clocks (core clock and peripheral clock) to have a common rising edge. if the clock frequencies are 66 mhz for the peripheral and 100-mhz for the core, there is a common rising edge every three core clocks and every two peripheral clocks.
chapter 6 typical settings 111 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 6 typical settings table 16 lists typical msr settings for the AMD-751 system controller. table 16. AMD-751 ? system controller msr settings register func:reg bit description bios initialized value setup option required/ suggested setup option 0:0x10 31:25 agp base address high xxxxb no agp aperture size is selected in dev0:0xac[3:1] and has to be set before pci enumeration 24:0 base low, prefetchable, type, memory 0008h no base low (24:4) are hardwired to 0 0:0x14 31:12 gart memory mapped register base high xxxxh no assigned by pci enumeration 11:0 base low, prefetchable, type, memory 008h no base low (11;4) are hardwired to 0 0:0x18 31:24 reserved 0 23:2 pm2_blk i/o register base address xxxxh no assigned by pci enumeration. port has to be enabled by setting dev0: 0x84[7] to ? 1 ? 1 reserved 0 0 i/o space 1 no hardwired 0:0x40/41, 0:0x42/43, 0:0x44/45, 0:0x46/47, 0:0x48/49, 0:0x4a/4b 15:7 bank base address [31:23] ? starting address of the bank (at 8m byte boundary) xxh no according to memory installed
112 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 6:1 bank address mask [28:23] xh no used as the size of a bank 000001 ? 8m 000011 ? 16m 000111 ? 32m 001111 ? 64m 011111 ? 128m 111111 ? 256m 0 bank enable x no 0 ? if memory is not present 1 ? if memory is present 0:0x50, 0:0x51, 0:0x52 7 reserved 0h 6 bank(x+1) address mode x no 0 ? 16mbit x4, x8, x16 1 ? 64mbit x4, x8, x16 5 number of banks in bank(x+1) (internal dram banks on a dimm) xno 0 ? 2 banks 1 ? 4 banks 4:3 reserved 00 2 bank(x) address mode x no 0 ? 16mbit x4, x8, x16 1 ? 64mbit x4, x8, x16 1 number of banks in bank (x) (internal dram banks on a dimm) xno 0 ? 2 banks 1 ? 4 banks 0 reserved 0 0:0x54 31:25 reserved 24 idle cycle limit bit 2 0 no see bit[13:12] 23:22 sdram addrb drv clkout drv xxb yes 00 ? low 01 ? medium low 10 ? medium high 11 ? high table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 6 typical settings 113 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 21:20 sdram addra drv xxb yes 00 ? low 01 ? medium low 10 ? medium high 11 ? high 19:18 sdram cas[2:0], ras[2:0], we[2:0], cke[2:0], cs[5:0] drive xxb yes 00 ? low 01 ? medium low 10 ? medium high 11 ? high 17:16 sdram dqm drive 1 yes 00 ? low 01 ? medium low 10 ? medium high 11 ? high 15:14 page hit request before a non-page hit 10 no 00 ? 1cyc, 01 ? 4cyc 10 ? 32cyc, 11 ? 64cyc 13:12 idle cycle to wait before precharging the idle bank 01 no 000 ? 0 cyc 001 ? 8 cyc (deflt) 010 ? 12 cyc 011 ? 16 cyc 100 ? 24 cyc 101 ? 32 cyc 110 ? 48 cyc 111 ? rsvd 11:9 trc timing value 101 no 000 ? 3cyc, 001 ? 4cyc 010 ? 5cyc, 011 ? 6cyc 100 ? 7cyc, 101 ? 8cyc 110 ? rsvd, 111 ? rsvd 8:7 trp timing 00 no 00 ? 3cyc, 01 ? 2cyc, 1x ? 1cyc 6:4 tras timing 101 no 000 ? 2cyc 001 ? 3cyc 010 ? 4cyc 011 ? 5cyc 100 ? 6cyc 101 ? 7cyc 110 ? rsvd 111 ? rsvd 3:2 tcl (cas latency) 00 yes 00 ? 3cyc 01 ? 2cyc 10 ? rsvd 11 ? 4cyc table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
114 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 1:0 trcd (ras to cas latency) 10 yes 00 ? 1cyc 01 ? 2cyc 10 ? 3cyc 11 ? 4cyc 0:0x58 31:26 reserved 25 sdram init 1 no 24 sdram type (reserved for future use) 0 ? sdram, 1 ? esdram 0no esdram is not supported by the AMD-751 system controller 23 mode register status (read/write once) 0 ? off/done, 1 ? to set 0no 22:21 reserved 00b 20 burst refresh enable 0 ? no bursting refreshing, 1 ? queue up to 4 refreshes before issuing 0yes 19 largest burst length (for future use) 0 ? 8qw 1 ? 4qw 0no 18 ecc enable 0 ? disable 1 ? enable 0 yes disabled by default 17 : 16 refresh counter 00 ? 2k cycle 01 ? 1.5k cycle 10 ? 1k cycle 11 ? 512k c ycle 00b no 15:10 reserved 000000b 9:8 ecc status 00 ? no error 01 ? multi-bit error (serr) 10 ? single-bit error detected 11 ? single and multi-bit error (serr) 00b no 7:6 reserved 00b table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 6 typical settings 115 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 5:0 one hot encoded chipselect of request that generate the single or multi-bit error 00000b no 0:0x60 31 probe enable for cpu0 (0 ? disable, 1 ? enable) 1no 30 lck half c2m 0 no 29 lck half m2c 0 no 28 lck half prb 0 no 27:25 xca probe count 010b no default 24:22 xca read count 110b no default 21:19 xca write count 100b no default 18 halt disconnect enable 0 ? no amd athlon system bus disconnect following halt 1 ? perform amd athlon system bus disconnect after halt 0 yes setup item is for debugging only 17 stop grant disconnect enable 0 ? no amd athlon system bus disconnect following stopgrant 1 ? perform amd athlon system bus disconnect after stopgrant 1no 16:14 probe limit 000 ? 1 probe 001 ? 2 probes ? . 110 ? 7 probes 111 ? 8 probes (max) 111b no 111b table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
116 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 13:10 ack limit 0000 ? 1 un0acked command 0001 ? 2 ? . 1111 ? - 16 0011b read only processor sysacklimit = ack_limit + 1 9 bypass enable 1 ? system controller bypasses certain memory to processor pipe stages for optimal performance 0yes 8:7 sysdcout delay 00 ? rsvd 01 ? 1 clk 10 ? 2 clks 11 ? 3 clks 10b read only 6:3 sysdcin delay 1010b no read only 2 wr2rd 0 no read only 1:0 rd2wr 10b no read only 0:0x64 31 clkfwd offset 0 ? AMD-751 system controller delays assertion of data and clock for amd athlon system bus sysdata 1 ? no delay 0no 30:0 all read only bits 52321824h no read only 0:0x68 biu1 status/control (not used) 00000000h no 0:0x6c biu1 sip (not used) 00000000h no 0:0x70 31:11 reserved 0 no table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 6 typical settings 117 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 10 pci pipe enable 0 ? mro checks outstanding read probe before pci transactions 1 ? mro pipelines pci transactions 1noalways set 9 pci block write enable 0 ? biu performs rid/inv probes, forcing mro mwq to wait for data movement 1 ? biu performs nop/inv probes for pci full-block writes 1noalways set 8:6 arbitration mode (testing only) 000b no 5:2 memory read queue disable (testing only) 0000b no 1 memory write queue disable (testing only) 0no 0 reorder disable 0 ? mro reorders memory requests to optimize memory performance 1 ? no reordering 0no 0:0x80 31:18 reserved 0 17 biu1 present 0 read only 16 biu0 present 1 read only 15:8 first amd athlon system bus id 00h read only 7:0 who am i 00h read only table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
118 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 0:0x84 31:24 agp vga bios address decode bit31: 0d_c000 ? 0d_ffff bit30: 0d_8000 ? 0d_bfff ? bit24: 0c_0000 ? 0c_3fff 00h no 23:18 reserved 000000b 17 enable apc chaining 1 ? processor writes to apc are chained together 1yes 16 enable pci chaining 1 ? processor writes to pci are chained together 1yes 15 mda support x yes if mda is present and agp is present 14 pci write-post retry 0 ? no retry 1 ? enables retry on pci if there are pending posted write 0no 13 apci write post retry 0 ? no retry 1 ? enables apci if there are pending posted write 0no 12 dis rd data err 0 ? returns read data error to processor on master abort or target abort 1 ? AMD-751 system controller returns all ones on data read error 1no table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 6 typical settings 119 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 11 dis apc early probe 1 ? disable early snoop from agp master running a pci cycle to memory 0no 10 dis pci early probe 1 ? disable early probe request for write cycles from an external pci master 0no 9 dis agp arbiter pipelining 1 ? disable agp arbiter from pipelining grants onto bus 0no 8 southbridge lock disable 1 ? disable flushing function performed before granting bus to the sb. 0no 7 pm register enable 1 ? enables r/w accesses to pm register at 0:0x18 1 no acpi required 6 15m hole enable 0 ? disable memory hole at 15 ? 16m 1 ? enable a memory hole at 15 ? 16m 0yes 5 14m hole enable 0 ? disable memory hole at 14 ? 15m 1 ? enable a memory hole at 14 ? 15m 0yes 4 ev6 mode 1 ? enable pci decoding in ev6 mode 0no may be enabled to allow dma transfer at a0000 ? fffff table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
120 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 3 target latency timer disable 1 ? disable AMD-751 system controller target latency timer on both pci and agp ? s pci interfaces 0no 2 apcpreen 1 ? enables AMD-751 to prefetch data from sdram when a pci master on agp bus reads from main memory 1no 1 pcipreen 1 ? enables AMD-751 system controller to prefetch data from sdram when a pci master on pci bus reads from main memory 1no 0 parkpci 0 ? pci arbiter parks on processor accesses to pci 1 ? enables parking on an external pci master 1no 0:0x88 31:0 config status 02410004h read only 0:0xa0 31:0 agp capability identifier register 00100002h read only 0:0xa4 31:0 agp status register 0f000203h read only 0:0xa8 31:10 reserved 9 sideband addressing enable 0 ? disable 1 ? enable 0no 8 agp operation enable 0 ? agp operation ignored 1 ? enable agp operation 0yes table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 6 typical settings 121 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 7:6 reserved 0 5 greater than 4g address support 0 ? disable 1 ? enable 0no 4:2 reserved 1:0 agp data transfer mode 01b ? 1x 10b ? 2x 0 no power on default 0:0xac 31:17 reserved 000h 16 vga isa address decoding 0 ? no isa aliasing on address [15:0] 1 ? force AMD-751 system controller to alias isa address [15:0] 1yes 15:4 reserved 000h 3:1 agp aperture size 000 ? 32mb 001 ? 64mb 010 ? 128m b 011 ? 256mb 100 ? 512m b 101 ? 1gb 110 ? 2gb 000b yes 0 agp aperture base address enable 0 ? disable register 0:0x10 (bar0) 1 ? enable register 0:0x10 (bar0) 0yes1 ? if agp is enabled in setup page 0:0xb0 31:21 reserved 20 agp read buffer size 0 ? 64qw 1 ? 32qw 0no table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
122 typical settings chapter 6 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 19 non-gart snoop 0 ? agp address falling outside gart do not cause probes 1 ? enable probes 0no 18 post gart queue size 0 ? 8 entries 1 ? 4 entries 0no 17 gart page directory cache enable 0 ? disable 1 ? enable 0no 16 gart index scheme control 0 ? two-level mode 1 ? one-level mode 0no 15:8 reserved 7 processor/agp read/write sync enable 0 ? no synchronization 1 ? AMD-751 system controller ensures that all writes to gart range from processor to memory are retired before initiating processor-to-agp cycle 0no 6:0 reserved 1:0x00 ~ 1:0x3f pci to pci bridge config spaces bios assigns this p-to-p bridge as bus 1 and sets memory and i/o base/limit according to p-to-p bridge spec if agp video is installed no table 16. AMD-751 ? system controller msr settings (continued) register func:reg bit description bios initialized value setup option required/ suggested setup option
chapter 7 configuration registers 123 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 7 configuration registers all of the many options available on the AMD-751 system controller are selected by writing to its pci configuration registers. these registers are usually programmed during system initialization and are not accessed during normal operation. however, some registers may require specific programming sequences during power-on self-test (post) to detect the type and size of installed memory. this section provides a description of the mechanism used to access the AMD-751 pci configuration registers as well as the location and functional details of each register. 7.1 pci configuration mechanism the AMD-751 system controller uses pci configuration mechanism #0 or #1 to convey and receive configuration data to and from the amd athlon processor. these mechanisms, described in pci local bus specification, revision 2.2 , employ i/o locations 0cf8h ? 0cfbh (address 1f_c000_0cf8h) to specify the target address and i/o locations 0cfch ? 0cffh (address 1f_c000_0cfch) for data to or from the target address. the target address includes the pci bus, device, function, and register numbers of the pci device. the AMD-751 system controller implements most registers as pci configuration registers. x86 software executes in and out instructions to i/o addresses of 0cf8h and 0cfch to access all configuration registers, which are translated by the processor into amd athlon system bus rdbytes and wrbytes commands, with the lower 24 bits of the address field containing the logical contents of the configaddr register (i/o address 0cf8h). configuration accesses in the AMD-751 system controller conform to the following rules: the AMD-751 is defined to be device 0. the idsel pin on every external pci device must be wired to one of the ad[31:12] lines, because logically ad[11] is assigned to device 0. device 0 accesses correspond to the processor-to-pci bridge registers listed in table 18 on page 126 and defined starting on page 130. device 1 accesses correspond to the pci-to-pci bridge registers listed in table 19 on page 128 and defined starting on page 161.
124 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information accesses can be byte, word, or doubleword in length and must be naturally aligned. the AMD-751 system controller creates type 0 and type 1 accesses as follows: if sysaddout[23:16] = 0 (bus number = 00h), a type 0 configuration cycle is generated and pci ad[1:0] = 00b. device number, sysadd[15:11] is decoded and asserted on pci ad[31:11] for idsel. if sysaddout[23:16] is not = 0 (bus number = 00h), a type 1 configuration cycle is generated and pci ad[1:0] = 01b. bus number and device number fields are passed onto the pci directly with no decoding. pci ad[31:24] = 00h. configuration address is a read-write port that responds only to doubleword accesses. byte or word accesses are passed on unchanged. bit 31 configuration space enable ? bit 31 enables the AMD-751 configuration space . 1 = the targeted pci device responds 0 = the i/o access is passed on unchanged bits 30 ? 24 reserved (always reads 0) bits 23 ? 16 pci bus number ? these bits select a specific system pci bus. the AMD-751 only supports one logical pci bus. bits 15 ? 11 device number ? this field defines which device is to be accessed in the system on the target pci bus. for type #0 configuration cycles, the AMD-751 system controller decodes this field and asserts the appropriate ad signal during the address phase to select the defined device. for type #1 configuration cycles, the AMD-751 passes this field through to the ad bus undecoded to select the defined device. devices are assigned a number by tying the device idsel# pin to a pci ad line. the AMD-751 system controller uses device 0 and device 1, which correspond to ad11 and ad12, respectively. device 0 (00000b) is the standard processor-to-pci bridge registers. device 1 (00001b) is the pci-to-pci bridge register set used to access the agp registers. note: ad11 and ad12 are reserved for the AMD-751 system controller and should not be accessed as idsel signals by any other pci device. configuration address ports 0cfbh ? 0cf8h 31 bit 30 ? bit 24 bit 23 ? bit 16 bit 15 ? bit 11 10 ? 8bit 7 ? bit 2 1 0 en reserved bus number device number function # register number 0 0 i/o address ocfbh i/o address ocfah i/o address ocf9h i/o address ocf8h
chapter 7 configuration registers 125 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 10 ? 8 function number ? these bits select the number of a specific function. the AMD-751 system controller is function 0. bits 7 ? 2 register number ? these bits specify the offset number of a register within the selected device space. the register number is a doubleword that, in conjunction with the pci byte enable lines c/be[3:0]#, specifies the configuration register offset number. bits 1 ? 0 reserved (always reads 0) configuration data is a read-write port that responds only to doubleword accesses. byte or word accesses are passed on unchanged. note: in the AMD-751 system controller, idsel is internally connected to ad11. other pci devices in a system must connect their idsel lines to a unique line in ad[31:12] and cannot use ad11. table 17 summarizes the i/o ports involved in pci configuration. configuration data ports 0cffh ? 0cfch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xxxxxxxxh table 17. configuration port register summary register name i/o address type default value size io_cntrl 0cf8h r/w 0000 0000h 32 io_data32 0cfch r/w 0000 0000h 32 io_odd_data16 0cfch r/w 0000h 16 io_even_data16 0cfeh r/w 0000h 16 io_0_data8 0cfch r/w 00h 8 io_1_data8 0cfdh r/w 00h 8 io_2_data8 0cfeh r/w 00h 8 io_3_data8 0cffh r/w 00h 8
126 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 7.2 register overview table 18 through table 20 summarize the AMD-751 system controller configuration register offsets, devices, default values after reset, and access types. access types are indicated as follows: rw read/write ro read only rwc read and/or write 1 ? s to clear individual bits rws read, but can only write a 1 to set the bit (a 0 does not reset the bit) rw0 read and write only 0 ? s for proper operation table 18. function 0, device 0 configuration registers offset cache control reset access description 01h ? 00h vendor id (amd) 1022h ro page 130 03h ? 02h device id single processor device 7006h ro page 130 05h ? 04h command 0004h rw page 130 07h ? 06h status 0210h rwc page 131 08h revision id nn * ro page 133 09h programming interface 00h ro page 133 0ah subclass code 00h ro page 133 0bh base class code 06h ro page 133 0ch reserved 00h ro page 133 0dh latency timer 00h rw page 134 0eh header type 80h ro page 134 0fh reserved 00h ro 13h ? 10h base address 0 (bar0) (agp memory) 0000_0008h rw page 135 17 h ? 14h base address 1 (bar1) (gart registers) 0000_0008h rw page 136 1bh ? 18h base address 2 (bar2) (pm2) 0000_0001h rw page 136 37h ? 34h capabilities 0000_00a0h ro page 137 41h ? 40h base address chip select 0 0000h rw page 137 43h ? 42h base address chip select 1 0000h rw page 138 45h ? 44h base address chip select 2 0000h rw page 138 47h ? 46h base address chip select 3 0000h rw page 138 note: * nn changes for each device revision. for example, 00h = revision a, stepping 1; 01h = revision a, stepping 2; 10h = revision b, stepping 1; 21h = revision c, stepping 2; etc.
chapter 7 configuration registers 127 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 49h ? 48h base address chip select 4 0000h rw page 139 4bh ? 4ah base address chip select 5 0000h rw page 139 50h sdram address mapping 1/0 00h rw page 140 51h sdram address mapping 3/2 00h rw page 140 52h sdram address mapping 5/4 00h rw page 141 53h reserved 00h ro 55h ? 54h dram timing 0000h rw page 143 57h ? 56h dram cs driver strength 0000h rw page 144 59h ? 58h dram ecc status 00h rw page 145 5bh ? 5ah dram mode/status 00h rw page 146 63h ? 60h biu status and control 0000_0cxxh rw page 147 67h ? 64h biu sip 0000_0000h rw page 149 69h ? 68h biu status 1 (reserved) 000xh rw page 150 6bh ? 6ah reserved 0000h rw 6fh ? 6ch reserved 0000_0000h rw 71 h ? 70h mro control register 0001h rw page 150 81h ? 80h who am i (whami) 00xxh rw page 151 83h ? 82h reserved 0000h ro 85h ? 84h pci arbitration control 0000h rw page 151 86h pci and apci chaining 00h rw page 154 87h agp vga bios mask 00h rw page 154 89h ? 88h config/status #1 0x0xh rw page 155 8bh ? 8ah config/status #2 000xh rw page 155 a3h ? a0h agp capability identifier 0100_0002h ro page 156 a7h ? a4h agp status 0f00_0203h ro page 157 abh ? a8h agp command 0000_0000h rw page 158 afh ? ach agp virtual address space size 0001_0000h rw page 158 b0h agp mode control register #1 00h rw page 159 b2h agp mode control register #2 02h rw page 160 table 18. function 0, device 0 configuration registers (continued) offset cache control reset access description note: * nn changes for each device revision. for example, 00h = revision a, stepping 1; 01h = revision a, stepping 2; 10h = revision b, stepping 1; 21h = revision c, stepping 2; etc.
128 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 19. function 0, device 1 configuration registers offset pci header reset access description 01h ? 00h vendor id 1022h ro page 161 03h ? 02h device id 7007h ro page 161 05h ? 04h agp/pci command 0000h rw page 161 07h ? 06h status 0220h ro page 163 08h agp revision id 00h ro page 164 09h programming interface 00h ro page 164 0ah subclass code 04h ro page 164 0bh base class code 06h ro page 164 0ch reserved 00h ro 0dh reserved 00h ro 0eh header type 81h ro page 165 0fh reserved 00h ro 18h primary bus number 00h rw page 165 19h secondary bus number 00h rw page 165 1ah subordinate bus number 00h rw page 165 1bh secondary latency timer 00h rw page 166 1ch i/o base register ffh rw page 166 1dh i/o limit register 0fh rw page 166 1fh ? 1eh agp/pci secondary status 0220h rwc page 167 21h ? 20h memory base 0000h rw page 168 23h ? 22h memory limit 0000h rw page 168 25h ? 24h agp/pci prefetchable memory base 0000h rw page 169 27h ? 26h agp/pci prefetchable memory limit 0000h rw page 169 30h i/o base 00h rw page 169 32h i/o limit 00h rw page 170 37h ? 34h reserved 0000_0000h ro 3dh ? 3ch interrupt control 0000h rw page 170 3fh ? 3eh pci-to-pci bridge control 0000h rw page 171
chapter 7 configuration registers 129 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information table 20. memory space configuration registers (bar1 + n) offset pci header reset access description 01h ? 00h features and capabilities 0301h ro page 173 03h ? 02h enable and status 0000h ro page 174 07h ? 04h agp gart base address 0000_0000h rw page 175 0bh ? 08h gart cache size 0000_0010h ro page 175 0fh ? 0ch gart cache control 0000_0000h rw page 176 13h ? 10h gart entry control 0000_0000h rw page 176 table 21. power management configuration registers (bar2 + n) offset pci header reset access description 01h ? 00h pm2 (power management) 0000h rw page 177
130 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 7.3 function 0, device 0 registers (processor-to-pci bridge, memory controller, etc.) this read-only value is defined as 1022h. this read-only value of 7006h represents the AMD-751 system controller single processor device. bits 15 ? 10 reserved (always reads 0) bit 9 fast back-to-back cycle enable (always reads 0) ? fast back-to-back cycles are not supported. 0 = fast back-to-back transactions only allowed to the same agent bit 8 serr# enable (rw) ? this bit does not affect the setting of bit 14 in offset 07h ? 06h. 0 = serr# output driver disabled (default) 1 = serr# output driver enabled note: if a system error is detected, serr# can be asserted by either the pci master or the amd-756 peripheral bus controller. bit 7 address/data stepping (always reads 0) 0 = device never uses stepping vendor id device 0 offset 01h ? 00h bit 1514131211109 8 7654321bit 0 vendor id reset0001000000100010 device id device 0 offset 03h ? 02h bit 1514131211109 8 7654321bit 0 device id reset0111000000000110 command device 0 offset 05h ? 04h bits 15 ? 10 9 8 7654321bit 0 reserved fbbce serre step per vgaps mwic scmon iten memspc iospc reset000000 0 0 0 0 0 00100
chapter 7 configuration registers 131 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 6 parity error response enable (always reads 0) 0 = do not report parity errors in status register offset 06 bit 8 (default) 1 = enable pci parity response in status register offset 06 bit 8 (not supported) bit 5 vga palette snoop (always reads 0) 0 = palette accesses generate normal pci cycles bit 4 memory write-and-invalidate command (always reads 0) ? this feature increases overall performance by eliminating cache writebacks when a pci initiator writes to the address of a modified line. 0 = the AMD-751 system controller never generates mwi. the AMD-751 responds to mwi commands by generating the appropriate probe on the amd athlon system bus. bit 3 special cycle monitoring (always reads 0) 0 = special cycles not monitored bit 2 initiator enable (always reads 1) 1 = AMD-751 system controller can behave as bus initiator bit 1 memory space (rw) 0 = disable pci memory space (default) 1 = responds to pci memory space accesses bit 0 i/o space (always reads 0) ? the AMD-751 does not act as an i/o target. bit 15 dram parity error detected (always reads 0) ? the AMD-751 does not support parity checking. bit 14 serr# error (rwc) ? this bit is set whenever the AMD-751 system controller generates a system error and asserts serr#. 0 = no error signaled 1 = serr# error signaled. the AMD-751 has asserted the serr# pin (mbe, gart error, or serr# assertion on the agp bus). status device 0 offset 07h ? 06h bit 15 14 13 12 11 10 ? 9 8 7 6 5 4 bits 3 ? 0 dpe serr# ria rta sta devsel# timing ppe fbbc udf 66 mhz cl reserved reset 0 0 0 0 0 0 1 0 0 0 0 10000
132 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 13 received initiator abort (rwc) ? this bit is set by a pci initiator when its transaction is terminated with initiator abort. 0 = pci transactions proceeding normally 1 = the AMD-751 system controller has detected that a transaction was terminated before completion bit 12 received target abort (rwc) ? the target issues a target abort when it detects a fatal error or cannot complete a transaction. this bit is set by simultaneously deasserting devsel# and asserting stop#. 0 = no abort received 1 = transaction aborted by target bit 11 signaled target abort (always reads 0) ? the AMD-751 system controller does not report target aborts. bits 10 ? 9 devsel# timing (always reads 01) ? this field indicates that the slowest devsel# timing is medium. bit 8 pci parity error detected (always reads 0) ? the AMD-751 does not support parity checking. 0 = no parity error detected/not supported bit 7 fast back-to-back capability (always reads 0) ? the AMD-751 can accept fast back-to-back transactions only if they are from the same agent. bit 6 user-defined features (always reads 0) ? the AMD-751 does not support user-defined features . bit 5 66 mhz-capable pci bus (always reads 0) ? the AMD-751 system controller only supports the 33-mhz pci bus. 0 = 33-mhz pci bus support (default) 1 = 66-mhz pci bus support (not supported) bit 4 capabilities list (always reads 1) ? this bit indicates that the configuration space of this device contains a capabilities list. bits 3 ? 0 reserved (always reads 0)
chapter 7 configuration registers 133 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 7 ? 0AMD-751 ? system controller revision code (ro) ? the most-significant nibble indicates the die revision and the least-significant nibble represents the stepping. (for example, 00h = revision a, stepping 1; 01h = revision a, stepping 2; 10h = revision b, stepping 1; 21h = revision c, stepping 2; etc.) bits 7 ? 0 AMD-751 system controller programming interface (always reads 00h) ? this register is defined in different ways for each combination of base and subclass codes. it is undefined for this type of device. bits 7 ? 0 subclass code (always reads 00h) ? the pci-defined subclass code for a processor bridge is 00h. bits 7 ? 0 base class code (always reads 06h) ? the pci-defined base class code for a bridge device is 06h. bits 7 ? 0 reserved (always reads 00h) revision id device 0 offset 08h bit 7 6 5 4 3 2 1 bit 0 AMD-751 system controller chip revision and stepping code reset ???????? programming interface device 0 offset 09h bit 7 6 5 4 3 2 1 bit 0 programming interface reset00000000 subclass code device 0 offset 0ah bit 7 6 5 4 3 2 1 bit 0 subclass code reset00000000 base class code device 0 offset 0bh bit 7 6 5 4 3 2 1 bit 0 base class code reset00000110 reserved device 0 offset 0ch bit 7 6 5 4 3 2 1 bit 0 reserved reset00000000
134 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 7 ? 0 latency timer value (rw) ? this 8-bit binary value specifies the latency timer in units of pci bus clocks. 00000000 = 0 pci clocks 00000001 ? 11111111 = (8-bit binary value) x pci clocks bits 7 ? 0 pci header type (ro) ? the AMD-751 system controller pci header type is 80h, indicating a multifunction device. bits 7 ? 0 reserved (always reads 00h) latency timer device 0 offset 0dh bit 7 6 5 4 3 2 1 bit 0 latency timer values reset00000000 header type device 0 offset 0eh bit 7 6 5 4 3 2 1 bit 0 header type reset10000000 reserved device 0 offset 0fh bit 7 6 5 4 3 2 1 bit 0 reserved reset00000000
chapter 7 configuration registers 135 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information this register is used by system bios memory mapping firmware to allocate virtual address space for agp. bits 31 ? 25 size (rw) (default = 000000b ) ? bios firmware writes 1s to this field, then reads the field back to determine how much memory is required for agp. the meaning of the returned value, shown in table 22, is a memory allocation size identical to the value represented in device 0, offset ach, bits 3 ? 1. (see page 159). bits 24 ? 4 base address low (always reads 0) ? this field are cleared to indicate that the minimum allocated memory size is 32 mbytes. bit 3 prefetchable (always reads 1) ? this bit is set to indicate that the graphics memory area can be prefetched. bits 2 ? 1 type (always reads 0) ? these bits are cleared to indicate that this base register is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. bit 0 memory (always reads 0) ? this bit is cleared to indicate that this base address register maps into memory space. base address register 0 (bar0) device 0 offset 13h ? 10h bits 31 ? 25 bits 24 ? 4 bit 3 bits 2 ? 1bit 0 size base address low pre type mem reset000000000000000000000000 1000 table 22. size field versus agp memory allocation bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 memory allocated 111111132 mbytes 111111064 mbytes 1111100128 mbytes 1111000256 mbytes 1110000512 mbytes 11000001 gbytes 10000002 gbytes
136 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information this register is used by the agp driver software to set the memory location of the agp memory-mapped control registers. bits 31 ? 12 base address high (rw) (default = 000000h) ? this field is loaded by bios firmware to determine the base address a[30:11] of the memory-mapped agp registers (bar1). see page 173 for more information. bits 11 ? 4 base address low (always reads 0) ? this field is cleared to indicate that 4 kbytes is allocated to agp memory-mapped control registers and that the registers reside in a 4-kbyte boundary per the pci local bus specification, revision 2.2 . bit 3 prefetchable (always reads 1) ? this bit is set to indicate that this range can be prefetched. bits 2 ? 1 type (always reads 0) ? these bits are cleared to indicate that bar1 is 32 bits wide and mapping can be performed anywhere in the 32-bit address space. bit 0 memory (always reads 0) ? this bit is cleared to indicate that bar0 maps into memory space. bits 31 ? 24 reserved (always reads 0) bits 23 ? 2 pm2 block base address (rw) ? this field contains the base address of the power management register block. this field forms the upper part of bar2 containing a[31:10]. this field is loaded by bios firmware and specifies the base of the pm2_blk. bit 1 reserved (always reads 0) bit 0 i/o space (always reads 1) ? this bit indicates that the base address register maps to x86 i/o space. base address register 1 (bar1) device 0 offset 17h ? 14h bits 31 ? 12 bits 11 ? 4 bit 3 bits 2 ? 1bit 0 base address high base address low pre type mem reset000000000000000000000000 1000 base address register 2 (bar2) device 0 offset 1bh ? 18h bits 31 ? 24 bits 23 ? 2 1 0 reserved pm2_block base address [31:10] r i/o reset00000000000000000000000000000001
chapter 7 configuration registers 137 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 31 ? 8 reserved (always reads 0) bits 7 ? 0 cap_ptr (always reads a0h) ? this field contains the pci device 1 offset of the configuration register group in the AMD-751 system controller specifically reserved for agp functions. this register group is the first item in the new capabilities mechanism described in an amendment to the pci local bus specification, revision 2.1 . bits 15 ? 7 bank 0 base address a[31:23] (rw) ? these bits determine the base or start address of the bank 0 chip select. the bank 0 address mask bits determine which of the address bits are to be used by the compare logic to generate a chip select, depending on the size of the memory bank. note: logically, chip select programming would be described in the following way: (mem_cs[n] = true) if (a[31:23] and (not bank(n) mask)) = (bank(n) base and (not bank(n) mask)). bits 6 ? 1 bank 0 address mask a[28:23] (rw) ? these bits are anded with a[28:23] from the processor to determine the size of the memory bank (8 mbytes, 16 mbytes, etc.). note: the minimum bank size supported is 8 mbyte. bit 0 bank 0 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled note: bios firmware must configure the largest banks first as the lowest addressed memory, then increasing addresses with decreasing bank sizes available. capabilities pointer device 0 offset 37h ? 34h bits 31 ? 8 bits 7 ? 0 reserved cap_ptr reset00000000000000000000000010100000 base address chip select register 0 device 0 offset 41h ? 40h bits 15 ? 7bits 6 ? 10 bank 0 base address a[31:23] bank 0 address mask a[28:23] en reset0 0000 0 0 0 0 0000000
138 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 15 ? 7 bank 1 base address a[31:23] (rw) ? see base address chip select register 0 on page 137. bits 6 ? 1 bank 1 address mask a[28:23] (rw) ? see base address chip select register 0. bit 0 bank 1 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled. bits 15 ? 7 bank 2 base address a[31:23] (rw) ? see base address chip select register 0 on page 137. bits 6 ? 1 bank 2 address mask a[28:23] (rw) ? see base address chip select register 0. bit 0 bank 2 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled bits 15 ? 7 bank 3 base address a[31:23] (rw) ? see base address chip select register 0 on page 137. bits 6 ? 1 bank 3 address mask a[28:23] (rw) ? see base address chip select register 0. bit 0 bank 3 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled base address chip select register 1 device 0 offset 43h ? 42h bits 15 ? 7bits 6 ? 10 bank 1 base address a[31:23] bank 1 address mask a[28:23] en reset0000000000000000 base address chip select register 2 device 0 offset 45h ? 44h bits 15 ? 7bits 6 ? 10 bank 2 base address a[31:23] bank 2 address mask a[28:23] en reset0000000000000000 base address chip select register 3 device 0 offset 47h ? 46h bits 15 ? 7bits 6 ? 10 bank 3 base address a[31:23] bank 3 address mask a[28:23] en reset0000000000000000
chapter 7 configuration registers 139 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 15 ? 7 bank 4 base address a[31:23] (rw) ? see base address chip select register 0 on page 137. bits 6 ? 1 bank 4 address mask a[28:23] (rw) ? see base address chip select register 0. bit 0 bank 4 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled bits 15 ? 7 bank 5 base address a[31:23] (rw) ? see base address chip select register 0 on page 137. bits 6 ? 1 bank 5 address mask a[28:23] (rw) ? see base address chip select register 0. bit 0 bank 5 enable (rw) 0 = memory bank is disabled (default) 1 = memory bank enabled base address chip select register 4 device 0 offset 49h ? 48h bits 15 ? 7bits 6 ? 10 bank 4 base address a[31:23] bank 4 address mask a[28:23] en reset0000000000000000 base address chip select register 5 device 0 offset 4bh ? 4ah bits 15 ? 7bits 6 ? 10 bank 5 base address a[31:23] bank 5 address mask a[28:23] en reset0000000000000000
14 0 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 7 reserved (always reads 0) bits 6 cs1 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 5 number of banks in cs1 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks bit 4 ? 3 reserved (always reads 0) bit 2 cs0 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 1 number of banks in cs0 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks bit 0 reserved (always reads 0) bit 7 reserved (always reads 0) bit 6 cs3 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 5 number of banks in cs3 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks sdram address mapping control register 1/0 device 0 offset 50h bit 7 6 5 4 3 2 1 bit 0 reserved address mode 1 #banks 1 reserved address mode 0 #banks 0 reserved reset00000000 sdram address mapping control register 3/2 device 0 offset 51h bit 7 6 5 4 3 2 1 bit 0 reserved address mode 3 #banks 3 reserved address mode 2 #banks 2 reserved reset00000000
chapter 7 configuration registers 141 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 4 ? 3 reserved (always reads 0) bit 2 cs2 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 1 number of banks in cs2 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks bit 0 reserved (always reads 0) bit 7 reserved (always reads 0) bit 6 cs5 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 5 number of banks in cs5 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks bit 4 ? 3 reserved (always reads 0) bit 2 cs4 address mode (rw) ? this bit specifies the row and column addressing as shown in table 23 on page 142. bit 1 number of banks in cs4 (rw) ? this bit specifies the number of internal dram banks in this chip select. 0 = two banks (default) 1 = four banks bit 0 reserved (always reads 0) sdram address mapping control register 5/4 device 0 offset 52h bit 7 6 5 4 3 2 1 bit 0 reserved address mode 5 #banks 5 reserved address mode 4 #banks 4 reserved reset00000000
142 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information mode 0, 2 bank: ma13 = bank select mode 1, 2 bank: ma13 = bank select mode 1, 4 bank: ma[13:12] = bank select table 23. mapping processor address lines to memory address lines sdram reg 50h addr mode ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 row:col 0 16 mbit row column 11 11 12 pc 22 24 21 23 20 10 19 9 18 8 17 7 16 6 15 5 14 4 13 3 x4 (11:10) x8 (11:9) x16 (11:8) 1 64 mbit 128 mbit row column 12 12 11 11 12 24 27 23 pc 22 26 21 25 20 10 19 9 18 8 17 7 16 6 15 5 14 4 13 3 x4 (14:11) x8 (14:10) x16 (14:9) x32 (14:8)
chapter 7 configuration registers 143 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 15 ? 14 ph limit (rw) ? these bits specify the number of consecutive page-hit requests to allow before choosing a non-page-hit request. 00 = 1 cycle(default) 01 = 4 cycles 10 = 32 cycles (recommended safe configuration) 11 = 64 cycles bits 13 ? 12 idle cycle limit [1:0] (rw) ? these bits specify the number of idle cycles to wait before precharging an idle bank. (idle cycles are defined as cycles where no valid request is asserted to the mct.) idle cyle limit[2:0]* 000 = 0 cycle (default) 001 = 8 cycles (recommended safe configuration) 010 = 12 cycles 011 = 16 cycles 100 = 24 cycles 101 = 32 cycles 110 = 48 cycles 111 = disable idle precharge * see idle cyle limit [2] on page 144. bits 11 ? 9 trc bank cycle time value (rw) ? these bits specify the minimum time from activate to activate of the same bank. 000 = 3 cycles (default) 001 = 4 cycles 010 = 5 cycles 011 = 6 cycles 100 = 7 cycles 101 = 8 cycles (recommended safe configuration) 110 = reserved 111 = reserved bits 8 ? 7 trp sras precharge (rw) ? these bits specify the delay from precharge command to activate command. 00 = 3 cycle (default) (recommended safe configuration) 01 = 2 cycles 1x = 1 cycles dram timing register device 0 offset 55h ? 54h bit 1514131211109 8 7654321bit 0 phl icl[1:0] trc trp tras tcl trcd reset0000000000000000
144 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 6 ? 4 tras value (rw) ? these bits specify the minimum bank (sras[2:0]#) active time. 000 = 2 cycles (default) 001 = 3 cycles 010 = 4 cycles 011 = 5 cycles 100 = 6 cycles 101 = 7 cycles (recommended safe configuration) 110 = reserved 111 = reserved bits 3 ? 2 tcl sdram scas latency value (rw) ? these bits specify the delay from scas[2:0]# to data valid. 00 = 3 cycle (default) (recommended safe configuration) 01 = 2 cycles 10 = reserved 11 = 4 cycles bits 1 ? 0 trcd sras to scas latency value (rw) ? these bits specify the delay from the activation of a bank to the time that a read or write command is accepted. 00 = 1 cycle (default) 01 = 2 cycles 10 = 3 cycles (recommended safe configuration) 11 = 4 cycles bits 15 ? 9 reserved (always reads 0) bit 8 idle cycle limit [2] (rw) ? this bit, along with those described on page 143, specify the number of idle cycles to wait before precharging an idle bank. bits 7 ? 6 sdram address bus b and clkout drv (rw) ? this bit specifies driver strength selection for the sdram madb and clock signals. 00 = light load ? one single-sided dimm 01 = medium light load ? not used 10 = medium heavy load ? two single-sided dimms or one double-sided dimm 11 = heavy load ? two double-sided dimms dram cs driver strength register device 0 offset 57h ? 56h bit 1514131211109 8 7654321bit 0 reserved icl[2] address bus b drv address bus a drv controls drv dqm drv reset0000000000000000
chapter 7 configuration registers 145 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 5 ? 4 sdram address bus a drv (rw) ? this bit specifies driver strength selection for the sdram mada signals. 00 = light load ? one single-sided dimm 01 = medium light load ? not used 10 = medium heavy load ? two single-sided dimms or one double-sided dimm 11 = heavy load ? two double-sided dimms bits 3 ? 2 sdram controls drv (rw) ? these bits specify driver strength selections for sras[2:0]#, scas[2:0]#, mcke[2:0], cs[5:0]#, and we[2:0]# signals. 00 = drive strength selected low 01 = drive strength selected medium low (recommended setting) 10 = drive strength selected medium high 11 = drive strength selected high bits 1 ? 0 sdram dqm bus drv (rw) ? this bit specifies driver strength selection for the sdram dqm signals. 00 = drive strength selected low 01 = drive strength selected medium low (recommended setting) 10 = drive strength selected medium high 11 = drive strength selected high bits 15 ? 10 reserved (always reads 0) bits 9 ? 8 ecc status (rw) ? this field indicates the status of the dram error correcting code detect logic. an i/o write must clear both bits in this field before any new status can be recorded. 00 = no error (default) 01 = multiple bit error detected (serr# asserts) 10 = single bit error detected 11 = single and multiple bit error detected (serr# asserts) bits 7 ? 6 reserved (always reads 0) bits 5 ? 0 ecc cs status (ro) ? this field indicates the chip select where the ecc error occured. bit 0 indicates cs0, bit 1 indicates cs1, etc. dram ecc status register device 0 offset 59h ? 58h bit 1514131211109 8 7654321bit 0 reserved ecc status reserved failing ecc chip select reset0000000000000000
146 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 15 ? 10 reserved (always reads 0) bit 9 sdram init (rws) ? this bit is used to start the sdram initialization sequence. when set, this bit cannot be reset. bios code should first set sdram timing parameters and signal drive strength prior to initiating this bit. bit 8 sdram type (rw0) 0 = sdram (default) 1 = esdram (not supported by the AMD-751 system controller) bit 7 mode write enable (rw) ? this bit is used by the bios to set the dram mode register. tcl and large burst enable must be set before this bit is asserted (see page 144). the mct clears this bit when the mode register write is complete. 0 = write to dram mode register is disabled/done (default) 1 = mode register write enabled bits 6 ? 5 reserved (always reads 0) bit 4 burst refresh enable (rw) 0 = refresh requests are only queued if memory requests are currently being serviced (default) 1 = up to four refresh requests are queued before being sent to the mct bit 3 large burst enable (always reads 0) 0 = eight quadword burst (default) 1 = four quadword burst bit 2 ecc enable (rw) 0 = ecc disabled (default) 1 = ecc enabled bits 1 ? 0 cycles per refresh (rw) ? this field specifies the number of 100-mhz clock cycles between refresh request. 00 = 2048 cycles between refresh (default) 01 = 1536 cycles between refresh (recommended) 10 = 1024 cycles between refresh 11 = 512 cycles between refresh dram mode/status register device 0 offset 5bh ? 5ah bit 1514131211109 8 7654321bit 0 reserved sd init type mwe reserved bre r en cycles reset0000000000000000
chapter 7 configuration registers 147 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 31 probe enable (rw) ? when set, this bit allows probes to be sent to the processor. bits 30 ? 28 reserved (always rw0) ? this field must always be written as 000 for maximum performance. bits 27 ? 25 xca probe count (rw) ? this field is set by the bios firmware with the maximum number of consecutive amd athlon system bus grants for probe transfers allowed before the AMD-751 system controller forces another type of transfer to gain access to the amd athlon system bus. the count limit prevents one type of transfer from dominating the amd athlon system bus. the recommended value is 010b. bits 24 ? 22 xca read count (rw) ? this field is set by the bios firmware with the maximum number of consecutive amd athlon system bus grants for read transfers allowed before the AMD-751 forces another type of transfer to gain access to the amd athlon system bus. the count limit prevents one type of transfer from dominating the amd athlon system bus. the recommended value is 110b. bits 21 ? 19 xca write count (rw) ? this field is set by the bios firmware with the maximum number of consecutive amd athlon system bus grants for write transfers allowed before the AMD-751 forces another type of transfer to gain access to the amd athlon system bus. the count limit prevents one type of transfer from dominating the amd athlon system bus. the recommended value is 100b. bit 18 halt disconnect enable (rw) 0 = no disconnect after a halt special cycle (default) 1 = disconnect after a halt special cycle note: see acpi power states on page 108 for more information. biu control and status register device 0 offset 63h ? 60h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 probe enable reserved r/w xca probe count xca read count xca write count halt dscena sgdis ena probe limit reset0 0 0 0000000000 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 probe limit ack limit bypass enable dcout delay dcin delay wr2r d dly rd2wr delay reset0000110xxxxxxxx x
148 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 17 stop grant disconnect enable (rw) 0 = no disconnect after a stop grant special cycle (default) 1 = disconnect after a stop grant special cycle bits 16 ? 14 probe limit (rw) ? this field is set by the bios firmware with the maximum probes that the processor can handle. 000 = 1 probe (default) 001 = 2 probes 010 = 3 probes . . 111 = 8 probes bits 13 ? 10 ack limit (ro) ? bios firmware reads this field to determine how many outstanding ? un-acked ? amd athlon system bus commands can be sent to the AMD-751 system controller. 0000= 1 un-acked commands 0001= 2 un-acked commands 0010= 3 un-acked commands 0011= 4 un-acked commands (default) . . . 1111= 16 un-acked commands bit 9 bypass mode enable (rw) ? when set, the AMD-751 allows low-latency accesses to memory. the low-latency access ? bypasses ? internal fifos and arbiters when no pci or apci operations are pending. this mode is valid for use in amd athlon processor systems only. note: bypass mode is available in revision c and later of the AMD-751 system controller. in previous revisions, this bit was used as the rih enable control. rih probes are always disabled. bits 8 ? 7 dc out delay (ro) ? this field specifies the number of system (normally 100-mhz) clock cycles from a processor read command and the start of data. 00 = reserved 01 = 1 cycles 10 = 2 cycles 11 = 3 cycles
chapter 7 configuration registers 149 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 6 ? 3 dc in delay (ro) ? this field specifies the number of system (100-mhz) clocks from a processor write command and the start of data. 0000= 1 clock 0001= 2 clocks . . . 1111= 16 clocks bit 2 wr2rd delay (ro) ? this field specifies the number of amd athlon system bus cycles that are inserted between write and read transfers to allow the data bus to turn around bits 1 ? 0 rd2wr delay (ro) ? this field specifies the number of amd athlon system bus cycles that are inserted between read and write transfers to allow the data bus to turn around. bit 31 clock forward offset (rw) ? this affects the clock forwarded data bus timing: 0 = AMD-751 system controller delays the assertion of sdata [31:16] and [63:48] bits and appropriate clocks by approximately 1000ps. 1 = all data groups are forwarded at the same time (nominally aligned with a system clock edge) bits 30 ? 29 data fifo initialize count (ro) ? this field displays the value loaded by the initialization logic in the data receive fifo counters. bits 28 ? 27 address fifo initialize count (ro) ? this field displays the value loaded by the initialization logic in the address receive fifo counters. bits 26 ? 0 sip[27:1] serial initialization packet (ro) ? this field contains the values loaded into the processor during the amd athlon system bus connect protocol. the initial state depends on the initialization logic. biu sip register device 0 offset 67h ? 64h bit 31 bits 30 ? 29 bits 28 ? 27 bits 26 ? 0 clock fo data init cnt addr init cnt sip packet reset 0 init logic 000000000000000000000000000
150 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 15 ? 0 reserved ? reserved for dual processor implementation. bit s 15 ? 11 reserved (always reads 0) bit 10 pci pipeline enable (rw) ? this bit should be set to 1 for optimal operation. when clear, all pci tranfers are checked against outstanding processor read probes. those tranfers with matching block addresses are then stalled until the matching read probe is complete. when set, pci transfers are pipelined for highest performance. bit 9 pci block write fast enable (rw) ? this bit should be set to 1 for optimal operation. when set, the AMD-751 system controller sends an nop invalidate probe to the amd athlon processor for pci block writes and allows the pci block write to memory to continue. when clear, the AMD-751 sends a read-if-dirty invalidate probe to the processor and waits for the data to return from the processor cache before allowing the pci block write to memory. bit s 8 ? 6 reserved (rw0) ? these bits must remain 0 for proper operation. bit s 5 ? 2 memory request disable (rw) ? these bits are for testing purposes only. when set, these bits disable request entries in the memory read queue (mrq) (default 000). bit 1 memory write queue disable (rw) ? this bit is for testing purposes only. 0 = enables the request entry in the memory write queue (mwq) (default) 1 = disables the request entry in the mwq bit 0 reorder disable (rw) 0 = the memory request organizer (mro) reorders memory requests to optimize memory performance 1 = the mro does not reorder memory requests (default) biu 1 status register device 0 offset 69h ? 68h bit 1514131211109 8 7654321bit 0 reserved reset00xx00000000xxx0 mro control register device 0 offset 71h ? 70h bit 1514131211109 8 7654321bit 0 reserved pcipipe enable pciblk wrfen reserved memory request disable mwd rd reset00000 0 0000000001
chapter 7 configuration registers 151 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 15 ? 8 first amd athlon ? system bus id (ro) ? this field contains the id of the first processor to read this register. bits 7 ? 0 who am i (ro) ? this field returns the id of the processor that accesses it. bit 15 mda support (rw) ? this bit allows monchrome display adapters (mda) to be used simultaneously with agp display cards. use this bit in conjunction with the vga enable bit (see page 171) as follows: vga = 0, mda = 0 ? all vga and mda references go to the pci bus vga = 0, mda = 1 ? undefined vga = 1, mda = 0 ? mda only operations (i/o 3bfh) go to pci, all other graphics references to agp vga = 1, mda = 1 ? all mda references go to pci and all agp references go to agp mda address ranges are defined as follows: memory ? 0b0000h ? 0b7fffh i/o ? 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh bit 14 pci write-post retry (rw) ? when set, this bit enables retries on the pci if there are pending posted writes. bit 13 apci write-post retry (rw) ? when set, this bit enables retries on the apci if there are pending posted writes. bit 12 disable read data error (rw) ? when set, this bit disables the AMD-751 system controller from reporting a data read error to the processor if the bui cycle was aborted. instead, the AMD-751 then returns a data value of all bits equal to 1b. who am i (whami) register device 0 offset 81h ? 80h bit 1514131211109 8 7654321bit 0 first amd athlon ? system bus id whami resetxxxxxxxxxxxxxxxx pci arbitration control register device 0 offset 84h ? 85h bit 1514131211109 8 7654321bit 0 mda suprt pciw prtr apci wprtr disrd err disap ciep dispci ep agpa d sblkdi s pmre gena 15mh ole 14mh ole ev6 tltd ape ppe park reset0000000000000000
152 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 11 disable apci early probe (rw) ? when set, this bit disables the AMD-751 system controller from issuing an early cache snoop to the processor when an apci (agp bus) master requests a memory write cycle. in the default mode, as soon as the AMD-751 detects a memory write cycle from an external apci master, it sends a probe only request to the mro, which results in a processor snoop. bit 10 disable pci early probe (rw) ? this bit works exactly the same as bit 11, except that it affects pci master requests rather than apci requests. bit 9 agp arbiter pipelining disable (rw) ? this bit disables the agp arbiter from pipelining grants onto the bus. 0 = enabled (default) 1 = disable the agp arbiter from pipelining grants onto the bus bit 8 sb lock disable (rw) ? this bit controls the response of the AMD-751 system controller to a pci request by the amd-756 peripheral bus controller. 0 = the AMD-751 ensures that all previous requests from the biu and pci are flushed out before granting the amd-756 the pci bus 1 = disable the flushing of previous requests bit 7 power management register access enable (rw) ? this bit controls reading and writing to the power management register (bar2). 0 = accesses to the power management register address (bar2) are forwarded to the pci bus, which results in a pci master abort cycle (default) 1 = enable access to the power management register bit 6 15mbyte hole enable (rw) ? when set, this bit creates a ? hole ? in memory from 15 mbytes to 16 mbytes, and the pci decode logic does not assert a match for those addresses. bit 5 14mbyte hole enable (rw) ? when set, this bit creates a ? hole ? in memory from 14 mbytes to 15 mbytes, and the pci decode logic does not assert a match for those addresses. bit 4 ev6 mode (rw) ? when set, this bit indicates that the pci interface decodes memory hits in the ev6 mode. there are no memory holes and dma can be performed on any address that lies within the sdram map. 0 = x86 mode (default) 1=ev6 mode
chapter 7 configuration registers 153 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 3 target latency timer disable (rw) ? when the AMD-751 system controller acts as a pci target, it has a latency timer that retries the write cycle if its buffers are full for more than 8 bus clocks (16 clocks for the first transfer). 0 = enabled (default) 1 = disable the target latency timer on both the standard pci and agp pci interfaces bit 2 apci prefetch enable (rw) ? this bit enables the AMD-751 system controller to prefetch data from the sdram when a pci master on the agp bus reads from the main memory. 0 = prefetch disabled (default) 1 = prefetch enabled bit 1 pci prefetch enable (rw) ? this bit enables the AMD-751 to prefetch data from the sdram when a pci master on the standard pci bus reads from the main memory. 0 = prefetch disabled (default) 1 = prefetch enabled bit 0 park pci (rw) ? this bit controls where the arbiter defaults to when there is no request pending. sometimes this is referred to as processor-centric (parking on the processor) or memory-centric. generally, a processor-centric system has improved processor benchmarks and a memory-centric system has improved overall system performance. the philosophy in a memory-centric system is that the last requestor is most likely to be the next requestor. 0 = the arbiter parks on the processor only (default) 1 = enable parking for the pci master (recommended)
154 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 1 enable apci chaining ? this bit allows chaining of back-to-back write operations to apci (from the processor). only sequencially-addressed write transactions that do not cross 4-kbyte page boundaries can be combined into one bus burst transfer (chaining). bit 0 enable pci chaining ? this bit allows chaining of back-to-back write operations to pci (from the processor). only sequencially-addressed write transactions that do not cross 4-kbyte page boundaries can be combined into one bus burst transfer (chaining). note: enable apci chaining and enable pci chaining bits are available on the AMD-751 system controller revision c and later. in previous revisions, these bits are read-only and always read 0. bits 15 ? 8 agp vga bios address (rw) ? this field indicates the corresponding 16-kbyte segment or segments that contains the vga bios on the agp bus. the range of bit settings are as follows: bit 0 = address range 0xc0000h ? 0xc3fffh bit 1 = address range 0xc4000h ? 0xc7fffh bit 3 = address range 0xc8000h ? 0xcbfffh bit 4 = address range 0xcc000h ? 0xcffffh bit 5 = address range 0xd0000h ? 0xd3fffh bit 6 = address range 0xd4000h ? 0xd7fffh bit 7 = address range 0xd8000h ? 0xdbfffh bit 8 = address range 0xdc000h ? 0xdffffh each rw bit determines if accesses in the respective address range are forwarded from the primary to the secondary pci bus. when set, these bits indicate that the corresponding segment (16 kbytes) should be mapped to the agp pci (secondary) bus. one or more of these bits should be set if the agp graphics card has a bios. 0 = do not forward (default) 1=forward bits 7 ? 2 reserved (always reads 0) pci and apci chaining register device 0 offset 86h bit 7654321bit 0 reserved chaining enable reset00000000 agp vga bios mask register device 0 offset 87h bit 7 6 5 4 3 2 1 bit 0 dc d8 d4 d0 cc c8 c4 c0 reset00000000
chapter 7 configuration registers 155 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 15 ? 12 reserved (always reads 0) bits 11 ? 8 reserved for dual processor implementation bits 7 ? 4 reserved (always reads 0) bits 3 ? 0 processor divider (ro) ? this field contains the processor divider field supplied by the amd athlon system bus. together with the clk speed and the bus length fields, this field allows the AMD-751 system controller to properly program the amd athlon processor interface logic using the sip protocol. the default value comes from bus pins ad[3:0]. bits 15 ? 9 reserved (always reads 0) bit 8 processor bus threshhold (ro) ? this bit indicates the threshold range for the amd athlon system bus i/o cells. 0 = low threshold of between 1.35v to 1.9v 1 = high threshold of between 2.0v to 2.2v bits 7 ? 6 agp to core clock ratio (ro) ? this field indicates the ratio of the agp logic clock and the system clock used to run the biu and memory control logic. bit 6 is controlled by the pll divisor pin. bit 7 is hard wired to 0. 00 = agp clock to system clock ratio of 1.0 to 1.0 01 = agp clock to system clock ratio of 1.0 to 1.5 (production setting) 1x = reserved bits 5 ? 4 clock speed (ro) ? the default comes from the bus pins ad[31:30]. this field defines the speed of the system clock received by the AMD-751 system controller. 00 = system clock speed is 100 mhz (production setting) 01 = system clock speed is 66 mhz 10 = system clock speed is 90 mhz 11 = reserved config status#1 device 0 offset 89h ? 88h bit 1514131211109 8 7654321bit 0 reserved reserved reserved processor divider reset0000sba7sba6sba5sba40000sba3sba2sba1sba0 config status #2 device 0 offset 8bh ? 8ah bit 1514131211109 8 7654321bit 0 reserved procb trshld agp/coreclk ratio coreclk reserved length 0 reset0000000ad400plldvad31ad30xxad11ad10
156 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 3 ? 2 reserved for dual processor implementation bits 1 ? 0 amd athlon ? system bus length (ro) ? this field indicates the relative length of the amd athlon system bus trace routing on the motherboard. the default comes from bus pins ad[11:10]. 00 = short, non-amd athlon system bus design 01 = single amd athlon system bus slot, close 10 = far amd athlon system bus slot, used for dual processor configurations 11 = farthest length amd athlon system bus slot (dual processor designs) bits 31 ? 24 reserved (always reads 0) bits 23 ? 20 major revision of agp specification (ro) ? these bits indicate the agp-specification major revision to which the device conforms. 0000 = revision 0 0001 = revision 1 0010 = revision 2 note: see bits 19 ? 16 for an example. bits 19 ? 16 minor revision of agp specification (ro) ? these bits indicate the agp-specification minor revision to which the device conforms. 0000 = revision x.0 0001 = revision x.1 0010 = revision x.2 for example, if bits 23 ? 16 = 20h, the device conforms to agp-specification revision 2.0. bit 15 ? 8 next pointer (always reads 0) ? the pointer to the next item in the new capabilities linked list is set to null to indicate the last item in the list. bits 7 ? 0 capability identifier (always reads 02h) ? the default value 02h indicates agp as assigned by the pci special interest group. agp capability identifier device 0 offset a3h ? a0h bits 31 ? 24 bits 23 ? 20 19 18 17 16 bits 15 ? 8 76543210 reserved major revision minor revision next pointer capabilities identifier reset00000000000100000000000000000010
chapter 7 configuration registers 157 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 31 ? 24 maximum request depth (always reads 0fh) ? the read-only value of 0fh indicates that the AMD-751 system controller can handle a maximum of 16 agp requests. bits 23 ? 10 reserved (always reads 0) bit 9 sideband address (always reads 1) ? this bit is set to indicate that the AMD-751 supports sideband addressing. bits 8 ? 6 reserved (always reads 0) bit 5 4-gigabyte address space (ro) ? this bit reflects the setting of the command register, offset a8h ? abh, bit 5. 0 = address space is limited to four gbytes (default) 1 = address space can be greater than four gbytes bits 4 ? 2 reserved (always reads 0) bits 1 ? 0 transfer rate capability (always reads 11b) ? this field indicates that the AMD-751 supports both 1x and 2x data transfers. agp status device 0 offset a7h ? a4h 31 30 29 28 27 26 25 24 bits 23 ? 10 bit 9 bits 8 ? 65bits 4 ? 2bits 1 ? 0 maximum request depth reserved sbae reserved 4g reserved trc reset0000111100000000000 1 0000000 1 1
158 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 31 ? 10 reserved (always reads 0) bit 9 sideband address enable (rw) 0 = sba operations are disabled (default) 1 = sba operations are enabled bit 8 agp enable (rw) 0 = agp operations are ignored (default) 1 = agp operations are accepted bits 7 ? 6 reserved (always reads 0) bit 5 4g_ena (always reads 0) ? when this bit is 0, it indicates the address range is up to four gbytes. the AMD-751 system controller only supports 32-bit addressing. bits 4 ? 2 reserved (always reads 0) bits 1 ? 0 transfer rate select (rw) ? one bit must be set in this field and the other cleared to indicate the desired agp data transfer rate. 00 = reset condition (default) 01 = selects 1x transfer mode 10 = selects 2x transfer mode 11 = not allowed bits 31 ? 17 reserved (always reads 0) bit 16 vga isa address space (rw) 0 = address bits a[15:10] are used for decoding 1 = address bits a[9:0] are used for decoding (default) bits 15 ? 4 reserved (always reads 0) agp command register #2 device 0 offset abh ? a8h bits 31 ? 10 bit 9 bit 8 bits 7 ? 65bits 4 ? 2bits 1 ? 0 reserved sbae agpe reserved 4g reserved trs reset00000000000000000 0 0 0000000 0 0 agp virtual address space device 0 offset af ? ach bits 31 ? 17 16 bits 15 ? 4 3210 reset reserved vi reserved vas ge 00000000000000010000000000000000
chapter 7 configuration registers 159 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 3 ? 1 virtual address space (rw) ? this field defines the amount of virtual address space (vas) allocated to the gart by the system bios. during its memory mapping routine, the bios reads the graphics controller to determine the amount of graphics memory required and adjusts these bits accordingly. changing these bits automatically changes device 0, offset 10h, bits 30 ? 25 (see page 135). the operating system allocates the actual number of non-contiguous 4-kbyte blocks of physical system memory allocated to the gart. the total amount of allocated physical memory can never exceed the vas size. 000 = 32 mbytes virtual address space (default) 001 = 64 mbytes 010 = 128 mbytes 011 = 256 mbytes 100 = 512 mbytes 101 = 1 gbytes 110 = 2 gbytes bit 0 gart enable (rw) ? this bit determines whether or not the system bios allocates virtual address space for the gart. if the processor-to-pci bridge (device 0, offset 10h) bar0 is set to 0, no memory is allocated. the pci-to-pci bridge (device 1) capabilities pointer is set to point to the next item in the linked list, or null if there is no other item. this bit is set by the bios pci enumeration routines. system bios allocates virtual address space for the gart based upon the value in bits [3:1]. 0 = gart operations are not valid (default) 1 = gart operations are valid bit 7 sync enable (rw) 0 = no synchronization is guaranteed (default) 1 = the AMD-751 system controller enables all writes to the gart range from processor to memory to be completed before initiating processor-to-agp cycles, allowing synchronization between the processor and agp bits 6 ? 0 reserved (rw0) ? these bits must remain 0 for proper operation. agp mode control register #1 device 0 offset b0h 7bits 6 ? 0 synen reserved reset00000000
16 0 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 7 ? 5 reserved (always reads 0) bit 4 reserved (rw0) ? this bit must remain 0 for proper operation. bit 3 non-gart snoop enable (rw) 0 = when clear, agp addresses that fall outside of the gart range do not cause probes (default) 1 = when set, this bit forces agp accesses that are not in the gart range to initiate amd athlon system bus probes to the processor(s) bit 2 reserved (rw0) ? this bit is always set to 0 for proper operation. bit 1 gart page directory cache enable 0 = gart page directory cache disabled. 1 = gart page directory cache enabled (default). bit 0 config 1 level indexing 0 = two-level gart indexing mode (default). 1 = one-level gart indexing mode. agp mode control register #2 device 0 offset b2h 7654321bit 0 reserved r ngse r gpdce g1lm reset00000010
chapter 7 configuration registers 161 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 7.4 device 1 registers (agp and pci-to-pci bridge) these registers configure agp and secondary pci bus operation. this read-only value is defined as 1022h to indicate amd. this read-only value of 7007h represents the AMD-751 system controller pci-to-pci bridge in the single processor device. bits 15 ? 10 reserved (always reads 0) bit 9 fast back-to-back enable (always reads 0) ? this bit indicates that fast back-to-back transactions are only allowed to the same agent. bit 8 serr# enable (rw) ? this bit and bit 6 must be set to 1 to report address parity errors. aserr# is an input to the AMD-751 system controller. the AMD-751 receives aserr# in the agp timing domain and passes it onto the pci serr# so that the amd-756 peripheral bus controller may generate an interrupt. 0 = serr# driver disabled (default) 1 = serr# driver enabled note: if a system error occurs, serr# may be asserted by an agp master. bit 7 address stepping (always reads 0) ? this device does not support address stepping. vendor id device 1 offset 01h ? 00h bit 1514131211109 8 7654321bit 0 vendor id reset0001000000100010 device id device 1 offset 03h ? 02h bit 1514131211109 8 7654321bit 0 device id reset0111000000000111 agp/pci command device 1 offset 05 ? 04h bits 15 ? 10 9 8 7 6 5 4 3 2 1 bit 0 reserved fbbe serre as peen vps mwi sc aia amse iose reset000000 0 0 0 0 0 0 0 0 0 0
162 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 6 parity error enable (always reads 0) 0 = parity error checking is not supported bit 5 vga palette snoop (always reads 0) ? palette accesses generate normal pci cycles. palette snooping of agp devices is not supported. bit 4 memory write-and-invalidate (mwi) command (always reads 0) ? pci-to-pci bridges like the AMD-751 system controller implement this bit as read only. 0 = the AMD-751 does not generate mwi commands bit 3 special cycle (always reads 0) ? a pci-to-pci bridge never responds as a target to special cycle transactions. bit 2 agp initiator access (rw) ? this bit enables the agp initiator (graphics controller) to access memory and the system pci bus. 0 = disable master accesses from the apci bus (default) 1 = enables the AMD-751 to accept master accesses from the apci bus bit 1 agp memory space enable (rw) ? by default, the processor writes to graphics adapter memory on pci bus 0. setting this bit allows the processor (and pci masters) to write to graphics adapter memory on the agp bus. apci memory space is defined by device 1, offset 20 on page 168. 0 = primary pci bus (default) 1 = agp bus/secondary pci bus bit 0 i/o agp enable (rw) ? by default, the processor writes to graphics adapter i/o space on pci bus 0. setting this bit allows the processor to write to graphics adapter i/o space on the agp bus. 0 = primary pci bus (default) 1 = agp bus/secondary pci bus when set, the AMD-751 system controller forwards amd athlon system bus accesses that reference apci i/o space onto the apci. apci i/o space is defined by device 1, offset 1c on page 166.
chapter 7 configuration registers 163 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 15 dram parity error detected (always reads 0) ? the AMD-751 system controller does not support parity checking. bit 14 aserr# error detected (rwc) 0 = no error detected 1 = aserr# error detected. a device has asserted the aserr# pin. the AMD-751 then asserts serr#. bit 13 received initiator abort (ro) ? this bit is set by a pci initiator when its transaction is terminated with initiator abort. 0 = pci transactions proceeding normally 1 = the AMD-751 has detected that a transaction was terminated before completion bit 12 received target abort (ro) ? the target issues a target abort when it detects a fatal error or cannot complete a transaction. this bit is set by simultaneously deasserting devsel# and asserting stop#. 0 = no abort received 1 = transaction aborted by target bit 11 signaled target abort (always reads 0) ? this AMD-751 system controller never signals a target abort. bits 10 ? 9 devsel# timing (ro) ? this field indicates the devsel# timing. 00 = fast 01 = medium (the AMD-751 only implements this timing) 10 = slow 11 = reserved bit 8 pci parity error detected (always reads 0) ? the AMD-751 system controller does not support parity checking. bit 7 fast back-to-back capability (always reads 0) ? the AMD-751 can accept fast back-to-back transactions only if they are from the same agent. bit 6 user-defined features (always reads 0) ? the AMD-751 system controller does not support user-defined features . status device 1 offset 07h ? 06h bit 15 14 13 12 11 10 ? 9 8 765 bits 4 ? 0 dpe aserr# ria rta sta devsel# timing ppe fbbc udf 66 mhz reserved reset 0 0 0 0 0 0 1 0 0 0 1 00000
164 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 5 66 mhz-capable pci bus (always reads 1) ? the apci (agp) interface supports 66-mhz operation. bits 4 ? 0 reserved (always reads 0) bits 7 ? 0 AMD-751 system controller revision code (ro) ? 00h = revision a bits 7 ? 0 programming interface (always reads 0) ? 00h = bridge bits 7 ? 0 subclass code (always reads 04h) ? the pci-defined subclass code for a pci-to-pci bridge is 04h. bits 7 ? 0 base class code (always reads 06h) ? the pci-defined base class code for a bridge device is 06h. agp revision id device 1 offset 08h bit 7 6 5 4 3 2 1 bit 0 revision id reset00000000 programming interface device 1 offset 09h bit 7 6 5 4 3 2 1 bit 0 programming interface reset00000000 subclass code device 1 offset 0ah bit 7 6 5 4 3 2 1 bit 0 subclass code reset00000100 base class code device 1 offset 0bh bit 7 6 5 4 3 2 1 bit 0 base class code reset00000110
chapter 7 configuration registers 165 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 7 ? 0 header type (always reads 81h) bits 7 ? 0 primary bus number (rw) ? this field records the number of the pci bus to which the primary interface of the bridge is connected. the bridge uses this number to decode type 1 configuration transactions on the secondary interface that should be converted to special cycle transactions on the interface. bits 7 ? 0 secondary bus number (rw) ? this field records the number of the pci bus to which the secondary interface of the bridge is connected. the bridge uses this number to determine when to respond to type 1 configuration transactions on the primary interface and convert them to type 0 transactions on the secondary interface. bits 7 ? 0 subordinate bus number (rw) ? this binary number is the system-assigned number of the highest ranking pci bus subordinate to a pci bridge. this field records the number of the highest numbered pci bus that is behind (or subordinate to) a bridge. the bridge uses this field in conjunction with the secondary bus number register to determine when to respond to type 1 configuration transactions on the primary interface and to pass them on to the secondary interface. agp header type device 1 offset 0eh bit 7 6 5 4 3 2 1 bit 0 header type reset10000001 agp primary bus number device 1 offset 18h bit 7 6 5 4 3 2 1 bit 0 primary bus number reset00000000 agp secondary bus number device 1 offset 19h bit 7 6 5 4 3 2 1 bit 0 secondary bus number reset00000000 agp subordinate bus number device 1 offset 1ah bit 7 6 5 4 3 2 1 bit 0 subordinate bus number reset00000000
16 6 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 7 ? 0 secondary latency timer (rw) ? this 8-bit binary value specifies the latency timer for the secondary pci bus in units of pci bus clocks. 00000000 = 0 pci clocks 00000001 ? 11111111 = (8 bit binary value) x pci clocks bits 7 ? 4 i/o base address lower nibble (rw) ? these four bits determine a[15:12] of the lower boundary of the address range in which the AMD-751 system controller forwards i/o transactions from one interface to the other. a[31:16] are specified in device 1, offset 31h ? 30h (see page 169). the default of fh disables the forwarding of i/o transactions. bits 3 ? 0 i/o base decode width (ro) ? these bits are set to indicate that 32-bit address decoding is available for i/o. bits 7 ? 4 i/o limit address lower nibble (rw) ? these four bits determine a[15:12] of the upper boundary of the address range in which the AMD-751 system controller forwards i/o transactions from one interface to the other. a[31:16] are specified in device 1, offset 33h ? 32h (see page 169). bits 3 ? 0 i/o limit decode width (ro) ? these bits are set to indicate that 32-bit address decoding is available for i/o. agp secondary latency timer device 1 offset 1bh bit 7 6 5 4 3 2 1 bit 0 secondary latency timer reset00000000 i/o base register device 1 offset 1ch bit 7 6 5 4 3 2 1 bit 0 i/o base address lower nibble i/o base ro reset11111111 i/o limit register device 1 offset 1dh bit 7 6 5 4 3 2 1 bit 0 i/o limit address lower nibble i/o limit ro reset00001111
chapter 7 configuration registers 167 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 15 detected parity error (always reads 0) ? the AMD-751 does not support parity checking. bit 14 signaled system error (rwc) ? the AMD-751 system controller sets this bit when aserr# is sampled asserted by an agp device. it then asserts serr#. 0 = no error detected (default) 1 = system error on agp bit 13 received initiator abort (rwc) ? this bit is set by an agp initiator whenever its transaction is terminated with initiator abort. 0 = agp transactions proceeding normally 1 = the AMD-751, acting as a pci initiator on the agp bus, has terminated a transaction before completion bit 12 received target abort (rwc) ? the target issues a target abort when it detects a fatal error or cannot complete a transaction by simultaneously deasserting devsel# and asserting stop#. the AMD-751 sets this bit when it detects this condition on the secondary pci bus. 0 = no abort received 1 = transaction aborted by target bit 11 signaled target abort (always reads 0) ? the AMD-751 system controller does not terminate transactions with target aborts. bits 10 ? 9 devsel# timing (ro) ? this field defines the devesl# timing. 00=fast 01=medium (default). the AMD-751 only supports this timing. 10=slow 11=reserved bit 8 data parity error (always reads 0) ? the AMD-751 system controller does not support parity checking. bit 7 fast back-to-back capablility (always reads 0) ? the AMD-751 can accept fast, back-to-back transactions from the same agent only. agp/pci secondary status device 1 offset 1fh ? 1eh bit 15 14 13 12 11 bits 10 ? 9 876 5 bits 4 ? 0 dpe sse ria rta sta devsel# tmg dped fbbc udf 66 mhz reserved reset0000001000 1 00000
16 8 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 6 user-defined features (always reads 0) ? the AMD-751 does not support user-defined features . bit 5 66-mhz-capable pci bus (always reads 1) ? the maximum secondary pci bus operating speed is 66 mhz. bits 4 ? 0 reserved (always reads 0) bits 15 ? 4 memory base (rw) ? this register defines the base address of the nonprefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. bits [15:4] correspond to address bits [31:20]. the lower 20 bits of the address are assumed to be 00000h. the memory address range adheres to 1-mbytes alignment and granularity. bits 3 ? 0 reserved (always reads 0) bits 15 ? 4 memory limit (rw) ? this register defines the top address of the nonprefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. the lower 20 bits of the address are assumed to be 0fffffh. the memory address range adheres to 1-mbytes alignment and granularity. bits 3 ? 0 reserved (ro) (always reads 0) memory base device 1 offset 21h ? 20h bits 15 ? 4bits 3 ? 0 memory base reserved reset0000000000000000 memory limit device 1 offset 23h ? 22h bits 15 ? 4bits 3 ? 0 memory limit reserved reset0000000000000000
chapter 7 configuration registers 169 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 15 ? 4 memory base (rw) ? this register defines the base address of the prefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. bits [15:4] correspond to address bits [31:20]. the lower 20 bits of the address are assumed to be 00000h. the memory address range adheres to 1-mbyte alignment and granularity. bits 3 ? 0 reserved (always reads 0) bits 15 ? 4 memory limit (rw) ? this register defines the top address of the prefetchable address range used by the agp target (graphics controller) where control registers and fifo-like communication interfaces are mapped. bits [15:4] correspond to address bits [31:20]. the lower 20 bits of the address are assumed to be 0fffffh. the memory address range adheres to 1-mbyte alignment and granularity. bits 3 ? 0 reserved (always reads 0) bits 7 ? 0 i/o base (rw) ? this register defines the top address bits a[23:16] of a 24-bit i/o base address. processor addresses that fall between the base and limit specified in this register are passed to the agp/apci bus (when the enable bit in device 1, offset 04, bit 0 is set). agp/pci prefetchable memory base device 1 offset 25h ? 24h bits 15 ? 4bits 3 ? 0 prefetchable memory base reserved reset0000000000000000 agp/pci prefetchable memory limit device 1 offset 27h ? 26h bits 15 ? 4bits 3 ? 0 prefetchable memory limit reserved reset0000000000000000 i/o base device 1 offset 30h bit 7 6 5 4 3 2 1 bit 0 i/o base reset10000001
170 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 7 ? 0 i/o limit (rw) ? this register defines the top address bits a[23:16] of a 24-bit i/o limit address. bits 15 ? 8 interrupt pin (rw) default 00h ? this field indicates which interrupt pin the pci-to-pci bridge uses. this field is rw to allow bios software to program the required value. 00h = no interrupt channel assigned (default) 01h = inta# 02h = intb# 03h = intc# 04h = intd# 05h ? ffh = not allowed bits 7 ? 0 interrupt line (rw) ? this field is rw to allow bios software to program the required value. this register indicates to which input of the system interrupt controller the interrupt signal pin is connected. 00h = default 01h = int1 02h = int2 . . . 0fh = int15 10h ? feh = not allowed ffh = no interrupt channel assigned (default) i/o limit device 1 offset 32h bit 7 6 5 4 3 2 1 bit 0 i/o limit reset10000001 interrupt control device 1 offset 3dh ? 3ch bit 1514131211109876543210 interrupt pin interrupt line reset0000000000000000
chapter 7 configuration registers 171 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information note: although required by the pci-pci bridge specification, this register is not used. bits 15 ? 8 reserved (always reads 0) bit 7 fast back-to-back enable (always reads 0) ? fast back-to-back transactions to different devices on the secondary interface are not supported. bit 6 secondary bus reset (always reads 0) ? this bit is not implemented. bit 5 initiator abort mode (always reads 0) ? determines the behavior of the pci-to-pci bridge when a master abort termination occurs on either interface when the bridge is the master of the transaction. read transactions return all bits equal to 1b, and write data is accepted by the bridge and then dropped. a master abort is not reported. bit 4 reserved (always reads 0) bit 3 vga enable (rw) ? when this bit is set, the AMD-751 system controller decodes and forwards vga accesses to the secondary pci bus rather than the primary pci bus. vga accesses include memory accesses in the range a0000 ? bffffh and i/o addresses in the ranges 3b0h ? 3bbh and 3c0 ? 3dfh. 0 = vga accesses are forwarded to the primary pci bus (default) 1 = vga accesses are forwarded to the secondary pci bus bit 2 isa enable (rw) ? this bit modifies the response by the bridge to isa i/o addresses, which applies only to i/o addresses that are enabled by the i/o base and i/o limit registers and are in the first 64 kbytes of pci i/o address space (0000_0000h to 0000_ffffh). when set, the bridge blocks any forwarding from the primary pci bus to the secondary pci bus of i/o transactions addressing the last 768 bytes in each 1-kbyte block. in the opposite direction (secondary to primary), i/o transactions are forwarded if they address the last 768 bytes in each 1-kbyte block. 0 = forward all i/o addresses in the address range defined by the i/o base and i/o limit registers (default) 1 = block forwarding of isa i/o addresses in the address range defined by the i/o base and i/o limit registers in the first 64 kbytes of pci i/o address space (top 768 bytes of each 1-kbyte block) pci-to-pci bridge control device 1 offset 3fh ? 3eh bit 15141312bits 11109876543210 reserved fb2b sbr iam r vgae isae sen pee reset0000000000000000
17 2 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 1 serr# enable (rw) 0 = serr# assertions on the secondary bus are not forwarded to the primary bus (default) 1 = serr# assertions on the secondary bus are forwarded to the primary interface bit 0 parity error enable (always reads 0) ? (secondary bus) the AMD-751 system controller does not support parity checking.
chapter 7 configuration registers 17 3 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 7.5 memory-mapped control registers the AMD-751 system controller implements a set of memory-mapped registers to control agp functionality. the system bios determines the base address of these registers and loads that value in the bar1 configuration register, device 0, offset 14h (see page 136). bits 15 ? 12 reserved (always reads 0) bit 11 enable hang on invalid gart entries ? this bit is used as a test mode to allow the AMD-751 system controller to hang on invalid gart entries. this bit is for software debug purposes only. for normal operation, do not set this bit. note: the enable hang on invalid gart entries test mode is available on the AMD-751 system controller revision c and later. in previous revisions, this bit is read-only and always reads 0. bit 10 pci-to-pci capability (ro) ? this bit is cleared to indicate that the AMD-751 only implements those pci-to-pci bridge commands required to implement agp. (the AMD-751 does not implement a complete pci 2.2-compliant pci-to-pci bridge between the pci bus and agp.) bit 9 multiple pages capability (always reads 1) ? this bit is set to indicate that the AMD-751 system controller supports multiple gart page entries. bit 8 valid bit error capability (always reads 1) ? this bit is set to indicate that the AMD-751 supports the detection of valid bit errors. the controller detects an access to an invalid page by checking the valid bit for each page of the gart. bits 7 ? 0 revision id (always reads 01h) features and capabilities register bar1 + offset 01h ? 00h bits 15 ? 12 bit 11 bit 10 bit 9 bit 8 bits 7 ? 0 reserved ghng ppc mpc vc revision id reset0000001100000001
174 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bit 15 ? 12 reserved (always reads 0) bit 11 pci-to-pci status (always reads 0) ? this bit is cleared to indicate that the AMD-751 system controller only implements those pci-to-pci bridge commands required to implement agp. (the AMD-751 does not implement a complete pci 2.2-compliant pci-to-pci bridge between the pci bus and agp.) bit 10 gart cache status (ro) 0 = gart cache is disabled (default) 1 = gart cache has been enabled by software (see description of bit 2 below) bit 9 multiple page status (ro) ? this bit is always 0 for the AMD-751 revision c3 and later. 0 = variable number of pages per gart directory cache (gdc) entry are disabled. each gdc entry cached refers to one 4-kbyte page only. (default) 1 = variable number of pages per gdc entry are enabled. each gdc entry cached refers to multiple 4-kbyte pages. (not supported) bit 8 valid bit error status (ro) ? the AMD-751 system controller sets this bit when the gart attempts to access an invalid page. if valid bit error signalling is enabled (bit 0 is set), the system also asserts serr#. 0 = no error detected (default) 1 = valid bit error detected bits 7 ? 4 reserved (always reads 0) bit 3 pci-to-pci enable (always reads 0) ? this bit is cleared to indicate that the AMD-751 system controller only implements the pci-to-pci bridge commands required to implement agp. (the AMD-751 does not implement a complete pci 2.2-compliant pci-to-pci bridge between the pci bus and agp.) enable and status register bar1 + offset 03h ? 02h bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bits 7 ? 4 bit 3 bit 2 bit 1 bit 0 reserved pps gcs mps vbes reserved ppe gce ensb detect vbee reset0000000000000000
chapter 7 configuration registers 17 5 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bit 2 gart cache enable (rw) 0 = gart translation lookaside buffer ( tlb) entry caching disabled (default) 1 = gart tlb entry caching enabled bit 1 disable sb_sba detect logic (rw) ? setting this bit disables the automatic sb_sba strobe detect logic. for backwards compatibility, the power-on default condition for this bit is 0 (enable detect logic). bios and any driver that writes to this register should set this bit to a 1 (disable) state only on the AMD-751 revision c3 and later. note: enable sb_sba detect logic is available on the AMD-751 system controller revision c3 and later. this newly defined control bit replaces a previously existing control in this register, ? multiple pages enabled ? , which enabled multiple pages per gart entry. that feature is not supported and bit 9 always read 0. bit 0 valid bit error enable (rw) ? setting this bit enables assertion of serr# when a graphics device attempts to access a page in agp memory that is not valid (page fault), generating a valid bit error. 0 = serr# is not asserted on a valid bit error (default) 1 = serr# is asserted on a valid bit error bits 31 ? 12 base address high (rw) (default 00000h) ? these 20 bits correspond to the 20 most-significant bits of the 32-bit gart base address, which is aligned on a 4-kbyte page boundary. these 20 bits provide 4-kbyte resolution, the minimum allowable size of the gart. a value other than 0 defines a valid base address. bits 11 ? 0 reserved (always reads 0) bits 31 ? 0 cache size (always reads 02h) ? the AMD-751 system controller implements a gart cache that contains 16 entries, organized as 8-way, two set-associative. agp gart base address register bar1 + offset 07h ? 04h bits 31 ? 12 bits 11 ? 0 gart base address reserved reset00000000000000000000000000000000 gart cache size register bar1 + offset 0bh ? 08h bits 31 ? 0 gart cache size reset00000000000000000000000000000010
176 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information bits 31 ? 1 reserved (always reads 0) bit 0 gart cache invalidate (rw) default 0 ? the agp driver sets this bit to invalidate the entire gart cache. when the AMD-751 system controller samples the bit high, it invalidates the cache and clears the bit. bits 31 ? 12 gart entry offset (rw) (default 00000h) ? to invalidate or update an entry in the gart cache, bits 31 ? 12 are written with the most significant 20 bits of the virtual address. if this address is present in the gart cache, it is invalidated or updated based on the state of bits 1 ? 0. if the address written to bits 31 ? 12 is either outside of the gart aperture or not present in the gart cache, no action is taken. bits 11 ? 2 reserved (always reads 00h) bit 1 gart cache entry update (rw) (default 0) ? setting this bit forces the AMD-751 system controller to update the gart cache entry specified in bits a[31:12] with the current entry in the gart table in system memory. the update function is performed immediately following the write to this register. the bit is cleared when the update operation is completed. bit 0 gart cache entry invalidate (rw) (default 0) ? setting this bit forces the AMD-751 to invalidate the gart cache entry specified in bits [31:12] if they are present in the gart cache. the invalidate function is performed immediately following the write to this register. the bit is cleared when the invalidate operation is completed. note: bits 1 ? 0 must never be set (11b) simultaneously. 00 = no action (default) 01 = invalidate 10 = update 11 = not allowed gart cache control register bar1 + offset 0fh ? 0ch bits 31 ? 10 reserved inv reset000000000000000000000000000000 0 gart entry control register bar1 + offset 13h ? 10h bits 31 ? 12 bits 11 ? 2 bit 1 bit 0 gart entry offset reserved updt inv reset0000000000000000000000000000 0 0
chapter 7 configuration registers 17 7 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information bits 31 ? 1 reserved (always reads 0) bit 0 arbiter disable (rw) ? this bit is used to enable and disable the system arbiter. 0 = the system arbiter is enabled and the arbiter can grant bus ownership to other bus masters in the system (default) 1 = when this bit is high, the system arbiter is disabled and the boot processor (given in whami ? device 0, offset 80 ? see page 151) has ownership of the system. agp and pci masters are not granted ownership of the bus. pm2 (power management) bar2 + offset 04h ? 00h bits 31 ? 1bit 0 reserved arbd reset00000000000000000000000000000000
178 configuration registers chapter 7 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information
chapter 8 electrical data 179 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 8 electrical data 8.1 absolute ratings the AMD-751 system controller is not designed to operate beyond the parameters shown in table 24. w arning : the absolute ratings in table 24 and associated conditions must be adhered to in order to avoid damage to the AMD-751 system controller and motherboard. systems using the AMD-751 must be designed to ensure that the power supply and system logic board guarantee that these parameters are not violated. violation of the absolute ratings will void the product warranty . table 24. absolute ratings parameter minimum maximum comments v dd ? 0.5 v 3.6 v core and i/o supply ref_5v ? 0.5 v 5.5 v reference supply v dd > ref_5v 1.0 v 1ms max. excursion v pin sdram ? 0.5 v v dd + 0.5 v v pin processor ? 0.5 v 3.0 v v pin pci ? 0.5 v ref_5v + 0.5 v v pin agp ? 0.5 v v dd + 0.5 v t case (under bias) 0 c70 c t storage ? 55 c+125 c
18 0 electrical data chapter 8 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 8.2 operating ranges the AMD-751 system controller is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in table 25. note: the voltage applied to v dd should never exceed the voltage applied to ref_5v. table 25. operating ranges parameter minimum typical maximum comments ref_5v 4.5 v 5.0 v 5.5 v 5 volt reference v dd 3.14 v 3.3v 3.46 v core (+/ ? 5%) t case 0 c85 c
chapter 8 electrical data 181 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 8.3 dc characteristics table 26 shows the dc characteristics for the AMD-751 system controller. table 27 on page 182 shows the dc characteristics for the amd athlon system bus/AMD-751. table 26. dc characteristics symbol parameter description preliminary data comments min max v il input low voltage (lvttl inputs) ? 0.5 v 0.8 v v ih input high voltage (lvttl inputs) 2.0 v 5.5 v v ol output low voltage (lvttl outputs) 0.45 v v oh output high voltage (lvttl outputs) 2.4 v i ref_5v 5-v power supply current 1 ma i dd 3-v power supply current (dynamic) 1.1 a 1.5 a i li input leakage current 10 a i lo output leakage current 10 a i il input leakage current bias with pullup 40 a i ih input leakage current bias with pulldown ? 40 a c in input capacitance 10 pf c out output capacitance 15pf c out i/o capacitance 20pf
182 electrical data chapter 8 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 27. amd athlon ? system bus/AMD-751 ? system controller dc specification symbol parameter description minimum nominal maximum units notes vcccore dc supply voltage 1.3 1.5 1.7 v v ref dc input reference voltage (0.6*vcccore) ? 50 0.6*vcccore (0.6*vcccore) +50 mv 1 i vref dc reference current ? 50 ? 50 a2 v ih (dc) dc input high voltage vref + 100 ? vcccore + 300 mv v il (dc) dc input low voltage ? 300 ? vref ? 100 mv v ih (ac) ac input high voltage vref + 200 ? vcccore + 500 mv v il (ac) ac input low voltage ? 500 ? vref ? 200 mv v oh (dc) dc output high voltage vcccore ? vcccore + 300 mv v ol (dc) dc output low voltage ? 300 ? 400 mv v oh (ac) ac output high voltage vcccore ? vcccore + 500 mv v ol (ac) ac output low voltage ? 500 ? 400 mv i leak tristate leakage ? 10 ? 10 a i ih input high current ? 10 ? 10 a3 i il input low current ? 10 ? 10 a3 i ol output low current 33 ?? ma 3 notes: * see figure 34 on page 194 for more information about the test circuit. 1. v ref : ? v ref is nominally set by a (1%) resistor divider from vcccore. ? the suggested divider resistor values are 80.6 ohms over 121.0 ohms to produce a divisor of 060. ? given: vcccore = 1.6 v, v ref = 960mv (1.6 * 0.60). ? peak to peak ac noise on v ref (ac) should not exceed 2% of v ref (dc). 2. i vref should be measured at nominal v ref . 3. i ih , i il , and i ol are measured at v ih -min (dc), v il -max (dc), and v ol -max (dc) respectively.
chapter 8 electrical data 183 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 8.4 power dissipation table 28 shows typical and maximum power dissipation of the AMD-751 system controller during normal and reduced power states. the measurements are taken with the v dd shown. 8.4.1 thermal considerations to allow for proper cooling and to maintain the case temperature specified in table 24 on 179, the AMD-751 system controller requires a heatsink. table 29 and table 30 list recommended heatsinks and thermal materials, respectively. table 28. typical and maximum power dissipation clock control state typical @ 100 mhz maximum @ 100 mhz comments normal (thermal power) 4.3 w @ 3.3 v 5.25 w @ 3.5 v halt-disconnect 3.3 w @ 3.3 v 3.85 v @ 3.5 v with sysclk running table 29. heatsinks for the AMD-751 ? system controller vendor part number aavid 372924m02000 foxconn phc0802-071 table 30. thermal interface material for the AMD-751 ? system controller vendor part number chomerics t710 * furon fc1060 furon c960* furon c964 furon c965 bergquist 200g thermagon t-pcm708 thermagon t-pcm910 notes: * an adhesive is included for easy attachment
184 electrical data chapter 8 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information
chapter 9 switching characteristics 185 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 9 switching characteristics the AMD-751 system controller signal switching characteristics are presented in tables 31 through 37. valid delay, float, setup, and hold timing specifications are listed. all signal timings are based on the following conditions: the target signals are input or output signals that are switching from logical 0 to 1, or from logical 1 to 0. measurements are taken from the time the reference signal (aclk, pclk, sdram clk_in, sysclk or reset) passes through 1.5v to the time the target signal passes through 1.5v. parameters are within the range of those listed in ? operating ranges ? on page 180.
18 6 switching characteristics chapter 9 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 9.1 sysclk switching characteristics table 31 contains the switching characteristics of the sysclk input to the AMD-751 system controller for 100-mhz processor bus operation. these timings are all measured with respect to the voltage levels indicated by figure 31. table 32 on page 187 contains the switching characteristics of the a_clk input for 66-mhz pci bus operation. table 33 on page 187 contains the switching characteristics of the pclk input for 33-mhz pci bus operation. these timings are all measured with respect to the voltage levels indicated by figure 32 on page 187. the clk period stability specifies the variance (jitter) allowed between successive periods of the clk input measured at appropriate reference voltage. this parameter must be considered as one of the elements of clock skew between the AMD-751 and the system logic. figure 31. sysclk waveform table 31. sysclk switching characteristics for 100-mhz bus operation symbol parameter description preliminary data figure comments min max 1/t 2 frequency 100 mhz 31 t 3 /t 2 x 100 sysclk duty cycle 45% 55% 31 1.15v reference t 4 sysclk falling edge slew rate 1.0 v/ns 31 t 5 sysclk rising edge slew rate 1.0 v/ns 31 sysclk period stability 250 ps 1.15v reference 0.8 v 1.15 v t 5 t 1 t 4 1.5 v t 2 t 3
chapter 9 switching characteristics 187 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information figure 32. clk waveform table 32. a_clk switching characteristics for 66-mhz bus operation symbol parameter description preliminary data figure comments min max frequency 66 mhz t 2 a_clk high time 6.0 ns 32 t 3 a_clk low time 6.0 ns 32 t 4 a_clk fall time 0.15 ns 1.5 ns 32 t 5 a_clk rise time 0.15 ns 1.5 ns 32 a_clk period stability 250 ps 1.5v reference table 33. pclk switching characteristics for 33-mhz pci bus symbol parameter description preliminary data figure comments min max t 1 pclk cycle 30 ns 32 t 2 pclk high time 11.0 ns 32 t 3 pclk low time 11.0 ns 32 t 4 pclk fall time 1 v/ns 4v/ns 32 t 5 pclk rise time 1 v/ns 4v/ns 32 pclk period stability 250 ps 1.5v reference 0.8 v 1.5 v 2.0 v t 5 t 1 t 4 t 3 t 2
18 8 switching characteristics chapter 9 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 9.2 valid delay, float, setup, and hold timings the valid delay and float timings for output signals during functional operation are relative to the rising edge of the given clock. the maximum valid delay timings are provided to allow a system designer to determine if setup times can be met. likewise, the minimum valid delay timings are used to analyze hold times. the setup and hold time requirements for the AMD-751 system controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-751. figure 33 shows the relationship between the rising clock edge and setup, hold, and valid data timings. figure 33. setup, hold, and valid delay timings t su t h t vd t vd data in data out clk
chapter 9 switching characteristics 189 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 9.3 pci interface timings table 34 shows the pci interface timings. all of the timings are relative to pclk. table 34. pci interface timings symbol parameter description preliminary data figure comments min max t su ad[31:0] setup time 7 ns 33 preq#, req[3:0]# setup time 12 ns 33 setup time for frame# stop# trdy# devsel# irdy# c/be[3:0]# reset# 7 ns 33 t h ad[31:0] hold time 0 ns 33 hold time for frame# stop# trdy# devsel# irdy# c/be[3:0]# preq# req[3:0]# 0 ns 33 t vd ad[31:0] valid delay (address phase) 2 ns 11 ns 33 pad 12 (note) ad[31:0] valid delay (data phase) 2 ns 11 ns 33 pad 12 (note) valid delay for frame# stop# trdy# devsel# irdy# c/be[3:0]# gnt[3:0]# 2 ns 11 ns 33 pad 13 (note) pgnt# valid delay 2 ns 12 ns 33 t fd float delay for frame# stop# trdy# devsel# irdy# c/be[3:0]# 28 ns 33 note t pw reset# pulse width 2 clks 33 t lat req# to gnt# latency 3 clks 33 note: measurements are taken with no load for t min , and 50 pf for t max.
19 0 switching characteristics chapter 9 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 9.4 sdram interface timings table 35 shows the sdram interface timings. all of the following timings are relative to sysclk, except where noted. table 35. dram interface timing symbol parameter description preliminary data figure comments min max t su mdat[63:0] setup 2 ns 33 relative to sdram clk_in (note 3) meccd[7:0] setup 2 ns 33 t h mdat[63:0] hold 1 ns 33 relative to sdram clk_in (note 3) meccd[7:0] hold 1 ns 33 t vd sdram clk_out valid delay 2 ns 6 ns 33 pad (note 1 and note 2) cs[5:0]# valid delay 2 ns 6 ns 33 pad (note 1 and note 2) mcke[2:0] valid delay 2 ns 6 ns 33 pad (note 1 and note 2) dqm[7:0]# valid delay 2 ns 6 ns 33 pad (note 1 and note 2) sras[2:0]# valid delay 2 ns 6 ns 33 pad (note 1 and note 2) scas[2:0]# valid delay 2 ns 6 ns 33 pad (note 1 and note 2) we[2:0]# valid delay 2 ns 6 ns 33 pad (note 1 and note 2) mada/madb[14:0] valid delay 2 ns 6 ns 33 pad (note 1 and note 2) md[63:0] valid delay 2 ns 6 ns 33 pad (note 1 and note 2) meccd[7:0] valid delay 2 ns 6 ns 33 pad (note 1 and note 2) t skew controls outputs ? 0.5 ns 1.5 ns relative to sdram clk_out (note 3) md[63:0] and meccd[7:0] outputs tbd ns 2.0 ns relative to sdram clk_out (note 3) notes: 1. measurements are taken with 50 ohm, ~ 30 pf load. 2. measurements for min. were taken with the drive strength set to light, and measurements for max. were taken with the drive st rength set to high. 3. by design, not tested.
chapter 9 switching characteristics 191 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 9.5 agp interface timings the agp interface can operate in two modes ? 1x and 2x. the timings for the 1x mode, shown in table 36, are relative to a_clk. the timings for the 2x mode, shown in table 37 on page 192, are relative to the respective strobe. table 36. agp 1x mode timings symbol parameter description preliminary data figure comments min max t su a_ad[31:0] setup time 5.5 ns note setup time for a_frame# a_stop# a_trdy# a_devsel# a_irdy# a_c/be[3:0]# a_req# adstb[1:0] sba[7:0] sbstb rbf# 6 ns note t h a_ad[31:0] hold time 0 ns note hold time for a_frame# a_stop# a_trdy# a_devsel# a_irdy# a_c/be[3:0]# a_req# adstb[1:0] sba[7:0] sbstb rbf# 0 ns note t vd a_ad[31:0] valid delay 1 ns 6.0 ns note a_c/be[3:0]# valid delay 1 ns 5.5 ns note valid delay for a_frame# a_stop# a_trdy# a_devsel# a_irdy# a_gnt# 1 ns 5.5 ns note t fd float delay (active to float) 1 ns 14 ns note t on turn-on delay (float to active) 1 ns 6 ns note note: these signals are specified with a 10 pf load.
192 switching characteristics chapter 9 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 37. agp 2x mode timings symbol parameter description preliminary data figure comments min max t su a_ad[31:0] setup time relative to strobe 1 ns note setup time relative to strobe for a_frame# a_stop# a_trdy# a_devsel# a_irdy# a_c/be[3:0]# a_req# sba[7:0] rbf# 1 ns note t h a_ad[31:0] hold time relative to strobe 1 ns note hold time relative to strobe for a_frame# a_stop# a_trdy# a_devsel# a_irdy# a_c/be[3:0]# a_req# sba[7:0] rbf# 1 ns note t datava a_ad[31:0] valid delay after strobe 1.9 ns note t cbeva a_c/be[3:0]# valid delay after strobe 1.9 ns note t datavb a_ad[31:0] valid before strobe 1.7 ns note t cbevb a_c/be[3:0]# valid before strobe 1.7 ns note t fd float delay (active to float) 1 ns 12 ns note t on turn-on delay (float to active) 1 ns 9 ns note note: these signals are specified with a 10 pf load.
chapter 9 switching characteristics 193 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 9.6 amd athlon ? system bus timings table 38 shows the amd athlon system bus timings. figure 34 on page 194 shows the test circuit used to achieve the values in the table. table 38. amd athlon ? system bus/AMD-751 ? system controller ac specification group symbol parameter description minimum nominal maximum units notes clock forward group signals t nb-skew- sameedge output skew with respect to the same clock edge ?? 400 ps 1 t nb-skew- diffedge output skew with respect to a different clock edge ?? 1025 ps 1 t nb-su input data setup time 500 ?? ps 1,2 t nb-hd input data hold time 800 ?? ps 1,2 t rise signal or clock rise time 1 ? 3v/ns t fall signal or clock fall time 1 ? 3v/ns c data data pin capacitance 4 ? 12 pf c inclk input clock capacitance 4 ? 12 pf sync signals *3 t nb-sysclk- to-pad sysclk to synchronous signal output at pad (connect, clkfwdrst) 2400 ? 4800 ps 4,5 t nb-setup- to-sysclk input setup time for synchronous signal to sysclk (procrdy) 1500 ?? ps 4,5 t nb-hold-fro m-sysclk input hold time for synchronous signal to sysclk (procrdy) 1200 ?? ps 4,5 notes: * see figure 34 on page 194 for more information about the test circuit. 1. t nb-skew-sameedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to the same clock edge. t nb-skew-diffedge is the maximum skew within a clock forwarded group between any two signals or between any signal and its forward clock, as measured at the package, with respect to different clock edges. 2. input su and hld times are with respect to the appropriate clock forward group input clock. 3. the synchronous signals include procready, connect, and clkfwdrst. 4. this value is measured with respect to the rising edge of sysclkin. 5. test load ? 25pf.
194 switching characteristics chapter 9 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 34. test circuit vcccore 68 ? 68 ? vcccore package device under test package device under test 50 ? 1 max 50 ? 8 max 50 ? 1 max component component
chapter 10 i/o buffer characteristics 195 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 10 i/o buffer characteristics except for the amd athlon system bus, all of the AMD-751 system controller inputs, outputs, and bidirectional buffers are implemented using a 3.3v buffer design. the amd athlon system bus runs at the processor core voltage (nominally 1.6v). amd has developed a model that represents the characteristics of the actual i/o buffers to allow system designers to perform analog simulations of the AMD-751 system controller signals that interface with the various system components. analog simulations are used to determine the time of flight of a signal from source to destination and whether the system signal quality requirements are met. signal quality measurements include overshoot, undershoot, slope reversal, and ringing. 10.1 i/o buffer model amd provides a model of the AMD-751 system controller i/o buffer for system designers to use in board-level simulations. this i/o buffer model conforms to the i/o buffer information specification (ibis) . the i/o model contains voltage versus current (v/i) and voltage versus time (v/t) data tables for accurate modeling of i/o buffer behavior. the following list characterizes the properties of the i/o buffer model: all data tables contain minimum, typical, and maximum values to allow for worst-case, typical, and best-case simulations, respectively. the pullup, pulldown, power clamp, and ground clamp device v/i tables contain enough data points to accurately represent the nonlinear nature of the v/i curves. in addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-751 system controller for those simulators that yield more accurate results based on this wider range. the rising and falling ramp rates are specified.
19 6 i/o buffer characteristics chapter 10 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information for most of the drivers, the min/typ/max v cc3 operating range is specified as 3.135v, 3.3v, and 3.6v, respectively. v il = 0.8v, v ih = 2.0v, and v meas = 1.5v for the amd athlon system bus, the min/typ/max v cc3 operating range is specified as 1.3v, 1.5v, and 1.8v, respectively. v il = 1.4v, v ih = 1.8v, and v meas = 1.6v the r/l/c of the package is modeled. the capacitance of the silicon die is modeled. the model assumes a test load resistance of 50 ? for all pins except for the amd athlon system bus, which assumes a 34 ? load. 10.2 i/o model application note for the AMD-751 system controller i/o buffer ibis model, go to the amd website at www.amd.com. for background information refer to the amd-k6 ? processor i/o model (ibis) application note , order# 21084. 10.3 i/o buffer ac and dc characteristics see chapter 9, ? switching characteristics ? starting on page 185 for the AMD-751 system controller ac timing specifications. see chapter 8, ? electrical data ? starting on page 179 for the AMD-751 system controller dc specifications.
chapter 11 pin designations 197 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 11 pin designations 12345678910111213 a mdat[47] meccd[4] meccd[5] scas[0]# dqm[0]# dqm[1]# sras[2]# mada[3] mada[5] mada[6] mada[10] mada[11] cs[5]# a b mdat[14] meccd[0] meccd[1] we[2]# dqm[4]# dqm[5]# sras[0]# mada[0] mada[2] mada[7] mada[8] mada[13] mada[14] b c mdat[44] mdat[13] vss scas[2]# we[0]# vss cs[1]# mada[1] vss mada[4] mada[9] vss cs[4]# c d mdat[10] mdat[42] mdat[11] mdat[15] scas[1]# cs[3]# cs[2]# sras[1]# madb[1] madb[3] madb[5] madb[6] madb[8] d e mdat[6] mdat[39] mdat[9] mdat[45] mdat[46] we[1]# clkout clkin madb[0] madb[2] madb[4] madb[9] madb[7] e f mdat[5] mdat[37] vss mdat[12] mdat[43] vss vss vdd vdd vdd f g mdat[34] mdat[3] mdat[4] mdat[40] mdat[41] vss g h saddout [14]# mdat[1] mdat[2] mdat[38] mdat[8] vdd h j saddout [13]# vss saddout [7]# mdat[36] mdat[7] vdd j k saddout clk# saddout [12]# saddout [9]# mdat[33] mdat[35] vdd k l saddout [8]# saddout [5]# saddout [6]# mdat[32] mdat[0] vss vss vss l m saddout [2]# vss saddout [10]# vterm[6] saddout [11]# vss vss vss m n saddout [3]# sdataou tclk[3]# scheck [6]# saddout [4]# sdata [55]# vss vss vss n p sdata [53]# sdata [49]# sdata [63]# sdata [54]# sdata [52]# vss vss vss p r sdatain- clk[3]# vss sdata [61]# vterm[7] sdata [50]# vss vss vss r t sdata [62]# sdata [60]# scheck [7]# sdata [51]# sdata [48]# vss vss vss t u sdata [59]# sdata [58]# sdata [57]# sdata [36]# sdata [46]# vss u v sdata [39]# vss sdata [37]# vterm[8] sdata [35]# vss v w sdata [56]# sdata [47]# sdata [38]# scheck [4]# sdata [34]# vss w y sdata [45]# sdata [44]# sdatain- clk[2]# sdata [33]# sdata [32]# vss y aa scheck [5]# vss sdataou tclk[2]# vterm[0] sdata [30]# vss vss vss vss vss aa ab sdata [43]# sdata [42]# sdata [41]# sdata [31]# sdatain- clk[1]# sdata [28]# sdata [27]# sdata [24]# sdata [1]# scheck [1]# sdata [10]# saddin [7]# saddin [8]# ab ac sdata [40]# sdataou tclk[1]# vss scheck [3]# sdata [29]# vterm[3] sdata [25]# sdata [15]# vterm[4] sdata [8]# sdataou tclk[0]# vterm[1] sdatain- val# ac ad vss sdata [23]# sdata [19]# vterm[5] sdata [17]# sdata [26]# scheck [0]# sdatain- clk[0]# sdata [12]# sdata [14]# saddin [5]# saddin [6]# saddin [4]# ad ae sdata [22]# sdata [21]# scheck [2]# sdata [18]# sdata [16]# vss sdata [4]# sdata [3]# vss sdata [11]# saddin [11]# vss saddin [10]# ae af vref sdata [20]# vss sdata [7]# sdata [6]# sdata [5]# sdata [2]# sdata [0]# sdata [13]# sdata [9]# saddin [2]# saddin [3]# saddin [9]# af 12345678910111213
19 8 pin designations chapter 11 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information 14 15 16 17 18 19 20 21 22 23 24 25 26 a mcke[2] dqm[2]# madb[12] meccd[3] mdat[49] mdat[19] mdat[52] mdat[54] mdat[24] mdat[26] mdat[28] mdat[29] mdat[31] a b mcke[1] dqm[3]# meccd[2] mdat[16] mdat[18] mdat[51] mdat[21] mdat[23] mdat[25] mdat[27] mdat[60] a_clk sysclk b c cs[0]# vss meccd[6] mdat[17] vss mdat[20] mdat[22] vss mdat[57] mdat[59] vss bypass# s_clkref c d madb[13] madb[14] mcke[0] dqm[7]# meccd[7] mdat[50] mdat[55] mdat[58] mdat[62] ref_5v s_clkout pclk rom_sda d e madb[10] madb[11] dqm[6]# mada[12] mdat[48] mdat[53] mdat[56] mdat[61] mdat[63] mdat[30] dcstop# reset# a_ad[1] e f vdd vdd vdd vss vss spare# a_clk out vss rom_sck a_ad[3] f g vss div# test# scan_en # a_ad[7] a_ad[4] g h vdd tristate# vdd_sys a_ad[8] adstb[0]# a_ad[6] h j vdd vdd_agp a_ad[0] vss a_ad[9] a_ad[10] j k vdd a_ad[2] a_ad[5] a_ad[14] a_ad[11] a_ad[12] k l vss vss vss a_c/be [0]# a_ad[13] a_par a_serr# a_c/be[1]# l m vss vss vss a_ad[15] a_stop# vss a_trdy# a_devsel# m n vss vss vss a_frame# a_ad[16] a_c/be [2]# a_vref a_irdy# n p vss vss vss a_ad[18] a_ad[20] a_ad[21] a_ad[19] a_ad[17] p r vss vss vss a_ad[22] a_c/be [3]# vss adstb[1]# a_ad[23] r t vss vss vss a_ad[26] a_ad[24] a_ad[29] a_ad[27] a_ad[25] t u vdd a_ad[30] a_ad[28] sba[5] sba[6] a_ad[31] u v vdd sba[3] sba[7] vss sbstb# sba[4] v w vdd ad[0] pipe# sba[1] sba[0] sba[2] w y vss c/be[0]# ad[6] st[0] st[2] rbf# y aa vdd vdd vdd vss vss par ad[11] vss a_req# st[1] aa ab connect gnt[2]# ad[27] gnt[3]# ad[26] ad[22] ad[18] frame# stop# ad[13] ad[2] ad[1] a_gnt# ab ac clk fwdrst vterm[2] req[2]# pgnt# ad[28] ad[24] ad[20] ad[16] trdy# ad[15] ad[5] ad[4] ad[3] ac ad saddin [13]# gnt[4]# gnt[1]# req[1]# vss ad[31] c/be[3]# vss c/be[2]# lock# vss ad[8] ad[7] ad ae saddin clk# vss req[4]# req[3]# wsc# ad[30] ad[25] ad[21] ad[17] devsel# c/be[1]# ad[12] ad[9] ae af saddin [14]# saddin [12]# procrdy gnt[0]# req[0]# preq# ad[29] ad[23] ad[19] irdy# serr# ad[14] ad[10] af 14 15 16 17 18 19 20 21 22 23 24 25 26
chapter 11 pin designations 199 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information AMD-751 ? system controller functional grouping ? 1 of 2 dram dram processor processor pci pin name pin no. pin name pin no. pin name pin no. pin name pin no. pin name pin no. cs[0]# cs[1]# cs[2]# cs[3]# cs[4]# cs[5]# dqm[0]# dqm[1]# dqm[2]# dqm[3]# dqm[4]# dqm[5]# dqm[6]# dqm[7]# mada[0] mada[1] mada[2] mada[3] mada[4] mada[5] mada[6] mada[7] mada[8] mada[9] mada[10] mada[11] mada[12] mada[13] mada[14] madb[0] madb[1] madb[2] madb[3] madb[4] madb[5] madb[6] madb[7] madb[8] madb[9] madb[10] madb[11] madb[12] madb[13] madb[14] mcke[0] mcke[1] mcke[2] mdat[0] mdat[1] mdat[2] mdat[3] mdat[4] mdat[5] mdat[6] mdat[7] mdat[8] mdat[9] mdat[10] mdat[11] mdat[12] mdat[13] mdat[14] mdat[15] mdat[16] mdat[17] c-14 c-7 d-7 d-6 c-13 a-13 a-5 a-6 a-15 b-15 b-5 b-6 e-16 d-17 b-8 c-8 b-9 a-8 c-10 a-9 a-10 b-10 b-11 c-11 a-11 a-12 e-17 b-12 b-13 e-9 d-9 e-10 d-10 e-11 d-11 d-12 e-13 d-13 e-12 e-14 e-15 a-16 d-14 d-15 d-16 b-14 a-14 l-5 h-2 h-3 g-2 g-3 f-1 e-1 j-5 h-5 e-3 d-1 d-3 f-4 c-2 b-1 d-4 b-17 c-17 mdat[18] mdat[19] mdat[20] mdat[21] mdat[22] mdat[23] mdat[24] mdat[25] mdat[26] mdat[27] mdat[28] mdat[29] mdat[30] mdat[31] mdat[32] mdat[33] mdat[34] mdat[35] mdat[36] mdat[37] mdat[38] mdat[39] mdat[40] mdat[41] mdat[42] mdat[43] mdat[44] mdat[45] mdat[46] mdat[47] mdat[48] mdat[49] mdat[50] mdat[51] mdat[52] mdat[53] mdat[54] mdat[55] mdat[56] mdat[57] mdat[58] mdat[59] mdat[60] mdat[61] mdat[62] mdat[63] meccd[0] meccd[1] meccd[2] meccd[3] meccd[4] meccd[5] meccd[6] meccd[7] scas[0]# scas[1]# scas[2]# sras[0]# sras[1]# sras[2]# we[0]# we[1]# we[2]# clkin clkout b-18 a-19 c-19 b-20 c-20 b-21 a-22 b-22 a-23 b-23 a-24 a-25 e-23 a-26 l-4 k-4 g-1 k-5 j-4 f-2 h-4 e-2 g-4 g-5 d-2 f-5 c-1 e-4 e-5 a-1 e-18 a-18 d-19 b-19 a-20 e-19 a-21 d-20 e-20 c-22 d-21 c-23 b-24 e-21 d-22 e-22 b-2 b-3 b-16 a-17 a-2 a-3 c-16 d-18 a-4 d-5 c-4 b-7 d-8 a-7 c-5 e-6 b-4 e-8 e-7 clkfwdrst connect procrdy reset# saddin[2]# saddin[3]# saddin[4]# saddin[5]# saddin[6]# saddin[7]# saddin[8]# saddin[9]# saddin[10]# saddin[11]# saddin[12]# saddin[13]# saddin[14]# saddinclk# saddout[2]# saddout[3]# saddout[4]# saddout[5]# saddout[6]# saddout[7]# saddout[8]# saddout[9]# saddout[10]# saddout[11]# saddout[12]# saddout[13]# saddout[14]# saddoutclk# scheck[0]# scheck[1]# scheck[2]# scheck[3]# scheck[4]# scheck[5]# scheck[6]# scheck[7]# sdata[0]# sdata[1]# sdata[2]# sdata[3]# sdata[4]# sdata[5]# sdata[6]# sdata[7]# sdata[8]# sdata[9]# sdata[10]# sdata[11]# sdata[12]# sdata[13]# sdata[14]# sdata[15]# sdata[16]# sdata[17]# sdata[18]# sdata[19]# sdata[20]# sdata[21]# sdata[22]# sdata[23]# sdata[24]# ac-14 ab-14 af-16 e-25 af-11 af-12 ad-13 ad-11 ad-12 ab-12 ab-13 af-13 ae-13 ae-11 af-15 ad-14 af-14 ae-14 m-1 n-1 n-4 l-2 l-3 j-3 l-1 k-3 m-3 m-5 k-2 j-1 h-1 k-1 ad-7 ab-10 ae-3 ac-4 w-4 aa-1 n-3 t-3 af-8 ab-9 af-7 ae-8 ae-7 af-6 af-5 af-4 ac-10 af-10 ab-11 ae-10 ad-9 af-9 ad-10 ac-8 ae-5 ad-5 ae-4 ad-3 af-2 ae-2 ae-1 ad-2 ab-8 sdata[25]# sdata[26]# sdata[27]# sdata[28]# sdata[29]# sdata[30]# sdata[31]# sdata[32]# sdata[33]# sdata[34]# sdata[35]# sdata[36]# sdata[37]# sdata[38]# sdata[39]# sdata[40]# sdata[41]# sdata[42]# sdata[43]# sdata[44]# sdata[45]# sdata[46]# sdata[47]# sdata[48]# sdata[49]# sdata[50]# sdata[51]# sdata[52]# sdata[53]# sdata[54]# sdata[55]# sdata[56]# sdata[57]# sdata[58]# sdata[59]# sdata[60]# sdata[61]# sdata[62]# sdata[63]# sdatainclk[0]# sdatainclk[1]# sdatainclk[2]# sdatainclk[3]# sdatainval# sdataoutclk[0]# sdataoutclk[1]# sdataoutclk[2]# sdataoutclk[3]# sysclk vref ac-7 ad-6 ab-7 ab-6 ac-5 aa-5 ab-4 y-5 y-4 w-5 v-5 u-4 v-3 w-3 v-1 ac-1 ab-3 ab-2 ab-1 y-2 y-1 u-5 w-2 t-5 p-2 r-5 t-4 p-5 p-1 p-4 n-5 w-1 u-3 u-2 u-1 t-2 r-3 t-1 p-3 ad-8 ab-5 y-3 r-1 ac-13 ac-11 ac-2 aa-3 n-2 b-26 af-1 ad[0] ad[1] ad[2] ad[3] ad[4] ad[5] ad[6] ad[7] ad[8] ad[9] ad[10] ad[11] ad[12] ad[13] ad[14] ad[15] ad[16] ad[17] ad[18] ad[19] ad[20] ad[21] ad[22] ad[23] ad[24] ad[25] ad[26] ad[27] ad[28] ad[29] ad[30] ad[31] c/be[0]# c/be[1]# c/be[2]# c/be[3]# devsel# frame# gnt[0]# gnt[1]# gnt[2]# gnt[3]# gnt[4]# irdy# lock# par pclk pgnt# preq# wsc# req[0]# req[1]# req[2]# req[3]# req[4]# serr# stop# trdy# w-22 ab-25 ab-24 ac-26 ac-25 ac-24 y-23 ad-26 ad-25 ae-26 af-26 aa-23 ae-25 ab-23 af-25 ac-23 ac-21 ae-22 ab-20 af-22 ac-20 ae-21 ab-19 af-21 ac-19 ae-20 ab-18 ab-16 ac-18 af-20 ae-19 ad-19 y-22 ae-24 ad-22 ad-20 ae-23 ab-21 af-17 ad-16 ab-15 ab-17 ad-15 af-23 ad-23 aa-22 d-25 ac-17 af-19 ae-18 af-18 ad-17 ac-16 ae-17 ae-16 af-24 ab-22 ac-22
200 pin designations chapter 11 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information AMD-751 ? system controller functional grouping ? 2 of 2 agp agp/pci vss vss vdd misc pin name pin no. pin name pin no. pin no. pin no. pin no. pin name pin no. adstb[0]# adstb[1]# pipe# rbf# sba[0] sba[1] sba[2] sba[3] sba[4] sba[5] sba[6] sba[7] sbstb# st[0] st[1] st[2] vdd_agp h-25 r-25 w-23 y-26 w-25 w-24 w-26 v-22 v-26 u-24 u-25 v-23 v-25 y-24 aa-26 y-25 j-22 a_ad[0] a_ad[1] a_ad[2] a_ad[3] a_ad[4] a_ad[5] a_ad[6] a_ad[7] a_ad[8] a_ad[9] a_ad[10] a_ad[11] a_ad[12] a_ad[13] a_ad[14] a_ad[15] a_ad[16] a_ad[17] a_ad[18] a_ad[19] a_ad[20] a_ad[21] a_ad[22] a_ad[23] a_ad[24] a_ad[25] a_ad[26] a_ad[27] a_ad[28] a_ad[29] a_ad[30] a_ad[31] a_c/be[0]# a_c/be[1]# a_c/be[2]# a_c/be[3]# a_clk a_devsel# a_frame# a_gnt# a_irdy# a_par a_req# a_serr# a_stop# a_trdy# a_vref j-23 e-26 k-22 f-26 g-26 k-23 h-26 g-25 h-24 j-25 j-26 k-25 k-26 l-23 k-24 m-22 n-23 p-26 p-22 p-25 p-23 p-24 r-22 r-26 t-23 t-26 t-22 t-25 u-23 t-24 u-22 u-26 l-22 l-26 n-24 r-23 b-25 m-26 n-22 ab-26 n-26 l-24 aa-25 l-25 m-23 m-25 n-25 ad-1 j-2 m-2 r-2 v-2 aa-2 c-3 f-3 ac-3 af-3 c-6 f-6 g-6 u-6 v-6 w-6 y-6 aa-6 ae-6 f-7 aa-7 aa-8 c-9 aa-9 ae-9 aa-10 l-11 m-11 n-11 p-11 r-11 t-11 c-12 l-12 m-12 n-12 p-12 r-12 t-12 ae-12 l-13 m-13 n-13 p-13 r-13 t-13 l-14 m-14 n-14 p-14 r-14 t-14 c-15 l-15 m-15 n-15 p-15 r-15 t-15 ae-15 l-16 m-16 n-16 p-16 r-16 t-16 c-18 ad-18 f-20 aa-20 c-21 f-21 g-21 y-21 aa-21 ad-21 c-24 f-24 j-24 m-24 r-24 v-24 aa-24 ad-24 h-6 j-6 k-6 f-8 f-9 f-10 f-17 aa-17 f-18 aa18 f-19 aa-19 h-21 j-21 k-21 u-21 v-21 w-21 a_clkout bypass# dcstop# div# ref_5v rom_sck rom_sda s_clkout s_clkref scan_en# spare# test# tristate# vdd_sys vterm[0] vterm[1] vterm[2] vterm[3] vterm[4] vterm[5] vterm[6] vterm[7] vterm[8] f-23 c-25 e-24 g-22 d-23 f-25 d-26 d-24 c-26 g-24 f-22 g-23 h-22 h-23 aa-4 ac-12 ac-15 ac-6 ac-9 ad-4 m-4 r-4 v-4
chapter 12 package specifications 201 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information 12 package specifications figure 35 and figure 36 on page 202 show the package specifications for the AMD-751 system controller. tables 39, 40, and 41, starting on page 203, contain information about the symbols shown in the figures. figure 35. bottom side view of package
202 package specifications chapter 12 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information figure 36. top and side views of package
chapter 12 package specifications 203 21910d ? august 1999 AMD-751 ? system controller data sheet preliminary information table 39. symbol notes symbol description 1 dimensions and tolerances conform to asme y14.5m ? 1994. 2 all dimensions are in millimeters. dimension ? b ? is measured at the maximum solder ball diameter on a plane parallel to datum c. datum c and the seating plane are defined by the spherical crowns of the solder balls. the number of peripheral rows and columns. ? s ? is measured with respect to datums a and b, and defines the position of the solder balls nearest the package centerlines. 7 conforms to jep-95, mo-151, issue 9, variation bal-2. the minimum flat area top side of the package is used for marking and pickup. the flatness specification applied to this area. any ejector marks must be outside of this area. optional features. 3 4 5 6 8 9 table 40. 492-pin pbga 35.0 mm by 35.0 mm package specifications symbol minimum nominal maximum description a 2.20 2.33 2.46 overall thickness a1 0.50 0.60 0.70 ball height a2 0.51 0.56 0.61 body thickness d 35.00 bsc. body size d1 31.75 bsc. ball footprint e 35.00 bsc. body size e1 31.75 bsc. ball footprint m 26 x 26 ball matrix size n 492 total ball count mr 5 number of rows b 0.60 0.75 0.90 ball diameter e1.27 bsc.ball pitch p 29.9 30.0 30.1 encapsulation area p1 28.0 minimum flat encapsulation area s 0.635 bsc. solder ball placement 5
204 package specifications chapter 12 AMD-751 ? system controller data sheet 21910d ? august 1999 preliminary information table 41. geometric tolerances symbol tolerance description aaa 0.15 coplanarity bbb 0.15 parallelism ccc 0.15 flatness
index 205 21910d ? august 1999 preliminary information index numerics 100-mhz bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 77 , 79 ? 80 , 110 , 190 clock . . . . . . . . . . . . . . . . . . . .1 , 14 , 79 , 110 , 150 , 152 ? 153 sdram . . . . . . . . . . . . . . . . . . . . . . . . 1 , 14 , 77 , 79 ? 80 , 110 133-mhz burst transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . 10 200-mhz bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 33-mhz pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 3d graphics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 renderings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4g_ena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4-gigabyte address space . . . . . . . . . . . . . . . . . . . . . . . . . . 161 66 mhz-capable pci bus . . . . . . . . . . . . . . . . . . . . . . . 136 , 168 66-mhz bus . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 168 , 172 , 191 a a_ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 34 , 40 ? 41 a_c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 35 , 41 a_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 , 35 a_devsel# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 a_frame# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 35 ? 37 , 97 a_gnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 , 42 a_irdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 37 a_par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 a_req# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 a_serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 38 aat (agp address translator) . . . . . . . . . . . . . . . . . . . .xxii , 64 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix ? xx absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 accelerated graphics port (agp). . . . . . . . . . . . . . . .see agp ack (acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii , 53 acpi (advanced configuration and power interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii , 5 , 112 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ? 113 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii ad[31:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 24 , 28 , 52 address decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 ? 47 , 69 space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 translation. . . . . . . . . . . . . . . . . . . . . . . see gart and ate address translation engine (ate). . . . . see gart and ate address/data stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 addressing, system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 adstb0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 advanced configuration and power interface (acpi). . . . . . . . . . . . . . . . . . . . . . . see acpi advanced programmable interrupt controller (apic). . . . . . . . . . . . . . . . . . . . . . see apic agp (accelerated graphics port) . . . . xxii , xxvi ? 2 , 4 ? 5 , 7 ? 8 , . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ? 11 , 13 ? 14 , 47 , 67 agp address translator (aat). . . . . . . . . . . . . . . see aat agp-to-memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 initiator access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 peripheral component interconnect (apci). . . see apci primary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 request queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ? 92 revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 secondary bus number . . . . . . . . . . . . . . . . . . . . . . . . . . 169 secondary latency timer . . . . . . . . . . . . . . . . . . . . . . . . 170 subordinate bus number . . . . . . . . . . . . . . . . . . . . . . . . 169 system dram interface (sdi) . . . . . . . . . . . . . . . . . . . . . 94 transaction queue (axq). . . . . . . . . . . . . . . . . . . .see axq virtual address space. . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 agp bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ? 11 a_ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 a_c/be#[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 a_frame#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 97 agp-only signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ? 96 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ordering rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 pipe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 34 ? 35 , 96 request queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 sba[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ? 35 st[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 agp/pci signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 a_ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 40 ? 41 a_c/be#[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 , 41 a_devsel# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 a_frame#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ? 37 a_gnt#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 a_irdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 37 a_par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 a_req# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 a_serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_stop#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 38 agp-only signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 a_clk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 , 35 a_gnt#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 adstb0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 pipe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 rbf# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 sba[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ? 42 sbstb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 st[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 alpha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 58 amd athlon processor . . . . . . . . . . . . xix , 1 , 6 ? 8 , 14 , 21 , 45 , . . . . . . . . . . . . . . . . . . 47 ? 49 , 52 ? 54 , 72 , 75 , 110 ? 111
206 index 21910d ? august 1999 preliminary information amd athlon system bus . . . . . 1 ? 2 , 7 , 45 , 47 ? 50 , 54 ? 56 , 58 , . . . . . . . . . . . . . . . . . . . 60 , 62 , 68 , 110 ? 112 , 127 , 135 , . . . . . . . . . . . . . . . . . . . . . . . . .152 ? 153 , 155 , 159 ? 160 , . . . . . . . . . . . . . . . . . . . . . . . . . 164 , 166 , 197 , 199 ? 200 amd publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi amd-750 chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 amd-756 peripheral bus controller . . . . . . . . . xxvi ? 1 , 6 , 14 , . . . . . . . . . . . . . . . . . . . . . . . 26 ? 29 , 45 , 48 ? 49 , 56 , 71 , . . . . . . . . . . . . . . . . . . . . . . 96 , 110 ? 112 , 134 , 156 , 165 apci (agp peripheral component interconnect) . . . . . . . . .xxii , 2 , 10 ? 11 , 63 ? 65 , 84 , 95 , . . . . . . . . . . . . . . . . .100 , 104 , 155 ? 158 , 166 , 168 , 173 api (application programming interface) . . . . . . . . . .xxii , 99 apic (advanced programmable interrupt controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii , 47 application programming interface (api). . . . . . . . . see api arbitration agp bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ? 96 pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ate (address translation engine) . . . . . . . . . xxii , 69 , 89 , 104 awq (pci/apci write queue) . . . . . . . . . . . . . . . . . . . .xxii , 53 axq (agp transaction queue) . . . . . . . . . . . . . . . xxii , 89 , 91 b bar (base address register) . . . . . . . . . . xxii , 13 , 47 , 50 ? 52 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 , 111 , 127 ? 181 base address high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 address low . . . . . . . . . . . . . . . . . . . . . . . . . . .139 ? 140 , 170 class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 base address register (bar). . . . . . . . . . . . . . . . . . see bar basic input/output system (bios). . . . . . . . . . . . . . see bios bios (basic input/output system) . . . . . . . . . . . xxii , 3 , 8 , 47 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ? 72 , 74 ? 76 , 110 bist (build-in self-test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii biu (bus interface unit) . . . . . . . . . . . . . . . . . . xxii , 12 , 62 , 64 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 functional units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 block diagram agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 amd-750 chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 AMD-751 system controller . . . . . . . . . . . . . . . . . . . . . . . . 12 bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . . . 53 mct (memory controller) . . . . . . . . . . . . . . . . . . . . . . . . . 67 memory queue arbiter (mqa) . . . . . . . . . . . . . . . . . . . . . 65 memory request organizer (mro) . . . . . . . . . . . . . . . . . 64 block writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 buffer characteristics, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . 199 buffer model, i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 buffers prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ? 62 , 82 , 85 built-in self-test (bist). . . . . . . . . . . . . . . . . . . . . . . see bist burst cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 62 , 72 , 82 bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi bus interface unit (biu). . . . . . . . . . . . . . . . . . . . . . . see biu byte merging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 , 85 c c/be[3:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ? 24 cache block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 gart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 , 102 l2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 , 83 operation, gart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 sdram type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 ? 145 size (agp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 snoops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 , 135 cap_ptr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 capability identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 cas[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 cas-before-ras. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 , 72 case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 cclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 characteristics i/o buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 i/o buffer ac and dc . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 chip select (cs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see cs clkfwdrst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 55 clock 100-mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 source-synchronized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 , 82 , 88 , 93 , 97 command address decoding . . . . . . . . . . . . . . . . . . . . . . . . 50 command queue (cq). . . . . . . . . . . . . . . . . . . . . . . . . see cq concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 configuration register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 space enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 configuration registers . . . . . . . . . . . . . . . . . . . . . . . 127 ? 181 agp capability identifier. . . . . . . . . . . . . . . . . . . . . . . . 160 agp command register #2 . . . . . . . . . . . . . . . . . . . . . . 162 agp gart base address register . . . . . . . . . . . . . . . . 179 agp header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 agp mode control register #1 . . . . . . . . . . . . . . . . . . . 163 agp mode control register #2 . . . . . . . . . . . . . . . . . . . 164 agp primary bus number . . . . . . . . . . . . . . . . . . . . . . . 169 agp revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 agp secondary bus number . . . . . . . . . . . . . . . . . . . . . 169 agp secondary latency timer. . . . . . . . . . . . . . . . . . . . 170 agp status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 agp subordinate bus number . . . . . . . . . . . . . . . . . . . . 169 agp vga bios mask . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 agp virtual address space . . . . . . . . . . . . . . . . . . . . . . 162 agp/pci prefetchable memory base . . . . . . . . . . . . . . . 173 agp/pci prefetchable memory limit . . . . . . . . . . . . . . 173 agp/pci secondary status . . . . . . . . . . . . . . . . . . . . . . . 171 base address chip select . . . . . . . . . . . . . . . . . . . . 141 ? 143 base address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 139 base address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . 140 base address register 2 . . . . . . . . . . . . . . . . . . . . . . . . . 140 base class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 biu 1 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 biu control and status . . . . . . . . . . . . . . . . . . . . . . . . . . 151 biu sip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 capabilities pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 , 165
index 207 21910d ? august 1999 preliminary information config status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 , 165 dram cs driver strength. . . . . . . . . . . . . . . . . . . . . . . . 148 dram ecc status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 dram mode/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 dram timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 enable and status register . . . . . . . . . . . . . . . . . . . . . . . 178 features and capabilities register. . . . . . . . . . . . . . . . . 177 gart cache control register . . . . . . . . . . . . . . . . . . . . 180 gart cache size register . . . . . . . . . . . . . . . . . . . . . . . 179 gart entry control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 i/o base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 i/o base register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 i/o limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 i/o limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 memory base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 memory limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 mro control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 pci and apci chaining . . . . . . . . . . . . . . . . . . . . . . . . . . 158 pci arbitration control . . . . . . . . . . . . . . . . . . . . . . . . . . 155 pci-to-pci bridge control . . . . . . . . . . . . . . . . . . . . . . . . 175 pm2 (power management). . . . . . . . . . . . . . . . . . . . . . . . 181 programming interface . . . . . . . . . . . . . . . . . . . . . . 137 , 168 revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 sdram address mapping control . . . . . . . . . . . . . 144 ? 145 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 167 subclass code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 , 165 who am i (whami) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 55 conventions, abbreviations, and references . . . . . . . . . . xix cpu clocks cclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 cq (command queue). . . . . . . . . . . . . . . . . . . . . . . . xxii , 2 , 53 cs (chip select) . . . . . . . . . . . . . .xxii , 3 , 68 ? 69 , 141 ? 145 , 149 cs[5:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 67 , 69 , 76 csq (system data and control queue) . . . . . . . . . xxii , 53 ? 54 d data block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 gdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 parity error detected . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 dcstop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ddr (double-data rate) . . . . . . . . . . . . . . . . . . . . . . . . . .xxii , 1 dec alpha. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dec alpha bus (ev6). . . . . . . . . . . . . . . . . . . . . . . . . see ev6 decoding address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 delay analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 detected parity error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 device 0 . . . . . . . . . . . . . . . . 52 , 127 , 134 ? 143 , 145 , 149 ? 150 , . . . . . . . . . . . . . . . . . . . . . . . . . 152 ? 157 , 159 ? 162 , 164 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 device 1 . . . . . . . . . . . . . . . . . . . . 52 , 127 , 165 ? 169 , 171 ? 176 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 device number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 devsel# . . . . . . . . . . . . . . . . . 23 ? 24 , 86 , 135 ? 136 , 167 , 171 timing (device 0). . . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 167 timing (device 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 dimm (dual inline memory module) . . . . . . . . . . xxii , 1 , 3 , 8 , . . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 30 , 33 , 63 , 68 ? 72 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ? 75 , 77 ? 79 , 81 direct memory access (dma). . . . . . . . . . . . . . . . . see dma direct random access memory (dram). . . . . . . see dram dma (direct memory access) . . . . . xxii , 29 , 84 , 98 , 112 , 156 don ? t-care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix double-data rate (ddr). . . . . . . . . . . . . . . . . . . . . . see ddr double-pumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 88 dqm[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 76 dram (direct random access memory). . . . . . . . . . xxii , 3 ? 4 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 8 , 10 controller cas[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 cs[5:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 dqm[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 33 ma[13:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 memory arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ras[5:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 , 76 refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 shadow ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 we[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 interface signals cs[5:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 dqm[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mada[14:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 madb[14:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mcke[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 33 mdat[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 meccd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 scas[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 we[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 dual inline memory module (dimm). . . . . . . . . . see dimm e ecc (error correcting code) . . . . . . . . . . .xxii , 2 ? 3 , 8 , 67 ? 69 , . . . . . . . . . . . . . . . . . . . . 71 ? 72 , 84 , 94 , 131 , 149 ? 150 eide (enhanced integrated device electronics) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii , 6 eisa (extended industry standard architecture). . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii , 84 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 enhanced integrated device electronics (eide). . . . . . . . . . . . . . . . . . . . . see eide enhanced programmable read only memory (eprom). . . . . . . . . . . . . . . . . . . see eprom eprom (enhanced programmable read only memory) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii error correction code (ecc). . . . . . . . . . . . . . . . . . . see ecc ev6 (dec alpha bus) . . . . . . . . . . . . . . . . . . . . . xxii , 155 ? 156 extended industry standard architecture (eisa). see eisa
208 index 21910d ? august 1999 preliminary information f fast back-to-back capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 cycle enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 , 165 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 mct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 fence command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 fid (frequency integer divisor) . . . . . . . . . . . . . . . . . .xxii , 61 fifo (first in, first out) . . . . . . . . . . . . . . . . xxii , 2 , 4 ? 5 , 7 ? 9 , . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 , 84 ? 85 , 89 , 92 , 97 first in, first out (fifo). . . . . . . . . . . . . . . . . . . . . . see fifo float timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 flush command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 frame# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ? 25 frequency integer divisor (fid). . . . . . . . . . . . . . . . . see fid full-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 112 function number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 functional operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ? 114 pin groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 ? 204 units biu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 g gart (graphics address remapping table) . . . . . . . . . . . . xxii , 5 , 11 , 47 , 52 , 67 , 83 , 86 , 88 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 ? 180 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 translation engine (ate). . . . . . . . . . . . . . . . . .see ate alternative scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 entry invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 entry update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .102 , 178 ? 180 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 conventional scheme . . . . . . . . . . . . . . . . . . . . . . . . . 99 ? 100 directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 cache (gdc) . . . . . . . . . . . . . . .xxii , 5 , 99 ? 102 , 104 , 178 entry offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 front end (gfe) . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxii , 102 memory space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table cache (gtc) . . . . . . . . . . . . . . xxii , 99 ? 102 , 104 , 109 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table walk (gtw) . . . . . . . . . . xxiii , 67 ? 68 , 102 , 104 ? 105 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 translation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 virtual address . . . . . . . . . . . . . . 98 ? 99 , 101 ? 102 , 104 , 109 gdc (gart directory cache). . . . . . . . . . . . . . . . . see gart geometric tolerances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 gfe (gart front end). . . . . . . . . . . . . . . . . . . . . . . see gart gnt[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 27 graphics memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 graphics address remapping table (gart). . . . see gart gtc (gart table cache). . . . . . . . . . . . . . . . . . . . . see gart gtw (gart table cache). . . . . . . . . . . . . . . . . . . . see gart h halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 112 hamming code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 high-speed transistor logic (hstl). . . . . . . . . . . . see hstl hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 hstl (high-speed transistor logic) . . . . . . . . . . . . . xxiii , 2 , 7 i i/o agp write enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 address lower nibble. . . . . . . . . . . . . . . . . . . . . . . . . 170 decode width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 buffer ac and dc characteristics . . . . . . . . . . . . . . . . . 200 buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 buffer model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 address lower nibble. . . . . . . . . . . . . . . . . . . . . . . . . 170 model application note . . . . . . . . . . . . . . . . . . . . . . . . . . 200 space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 iack (interrupt acknowledge) . . . . . . . . . . . . xxiii , 46 ? 47 , 51 ibis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 ide (integrated device electronics) . . . . . . . . . . . . . . xxiii , 26 imb (interrupt message bus) . . . . . . . . . . . . . . . . . . . xxiii , 29 industry standard architecture (isa). . . . . . . . . . . . . see isa initiator enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 integrated device electronics (ide). . . . . . . . . . . . . see ide interface levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 interrupt line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 interrupt acknowledge (iack). . . . . . . . . . . . . . . . see iack interrupt message bus (imb). . . . . . . . . . . . . . . . . . . see imb irdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 25 , 29 isa (industry standard architecture). . . . . . . . . . .xxiii , 6 , 26 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 , 162 , 175 j jedec (joint electron device engineering council) . . . . . . . . . . . . . . . . . . . . . . . xxiii , xxvi , 69 , 78 joint electron device engineering council (jedec). . . . . . . . . . . . . . . . . . . . .see jedec joint test action group (jtag). . . . . . . . . . . . . . . . see jtag jtag (joint test action group) . . . . . . . . . . . . . . . . . . xxiii , 14 l l2 cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 , 83 lan (large area network) . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii large area network (lan). . . . . . . . . . . . . . . . . . . . . . . . . xxiii latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 , 170 value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 least-recently used (lru). . . . . . . . . . . . . . . . . . . . see lru least-significant bit (lsb). . . . . . . . . . . . . . . . . . . . . see lsb legacy x86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 , 47 , 50 linking capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 lock#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 , 93
index 209 21910d ? august 1999 preliminary information low voltage transistor transistor logic (lvttl). . . . . . . . . . . . . . . . . . . . . . . see lvttl lru (least-recently used) . . . . . . . . . . . . . . . . . . . . . xxiii , 109 lsb (least significant bit) . . . . . . . . . . . . . . . . . . . . . . xxiii , 57 lvttl (low voltage transistor transistor logic) . . . . . . . . xxiii m ma (memory address) . . . . . . . . . . . . . . . . . . . . . . . . . xxiii , 79 ma[13:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 mada[14:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 madb[14:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 master abort mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 maximum request depth . . . . . . . . . . . . . . . . . . . . . . . . . . 161 mcke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 , 74 mcke[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 31 , 33 mct (memory controller) . . . . . . . . . xxiii , 12 , 63 ? 67 , 74 , 94 blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 md (memory data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii , 79 mda (monochrome display adapter) . . . . . . . . . . . . xxiii , 155 mdat[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 mdp (memory data path) . . . . . . . . . . . . . . . . . . . xxiii , 67 , 69 meccd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 memory . . . . . . . . . . . . . . . . . . . . . . . . . . xx , 2 ? 4 , 47 , 139 ? 140 agp write enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ? 173 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 controller (mct). . . . . . . . . . . . . . . . . . . . . . . . . . see mct data path (mdp). . . . . . . . . . . . . . . . . . . . . . . . . . . see mdp detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 dos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 high speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ? 173 main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 memory-mapped control registers . . . . . . . . . . . . . . . . 140 memory-to-agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 queue arbiter (mqa). . . . . . . . . . . . . . . . . . . . . . see mqa read queues (mrq) . . . . . . . . . . . . . . . . . . . . . . . see mrq read queues (mrq). . . . . . . . . . . . . . . . . . . . . . . . see mrq request arbiter (mra). . . . . . . . . . . . . . . . . . . . . see mra request organizer (mro). . . . . . . . . . . . . . . . . . . see mro request scheduler (mrs). . . . . . . . . . . . . . . . . . . see mrs sdram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 write queues (mwq). . . . . . . . . . . . . . . . . . . . . . .see mwq write selector (mws). . . . . . . . . . . . . . . . . . . . . . see mws write-and-invalidate command (device 0) . . . . . . . . . . 135 write-and-invalidate command (device 1) . . . . . . . . . . 166 memory address (ma). . . . . . . . . . . . . . . . . . . . . . . . . see ma memory data (md). . . . . . . . . . . . . . . . . . . . . . . . . . . . see md monochrome display adapter (mda). . . . . . . . . . . see mda most significant bit (msb). . . . . . . . . . . . . . . . . . . . see msb mqa (memory queue arbiter) . . . . . . . . . . . . . . . . xxiii , 63 , 65 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mra (memory request arbiter). . . . . . . . . . . . . . . xxiii , 67 ? 69 mrf (memory read fifo) . . . . . . . . . . . . . . . . . . . . . . . xxiii , 2 mrl (memory read line) . . . . . . . . . . . . . . . . . . . . . . xxiii , 4 , 9 mrm (memory read multiple) . . . . . . . . . . . . . . . . . xxiii , 4 , 9 mro (memory request organizer) . . . . . . . . . xxiii , 2 , 12 , 53 , . . . . . . . . . . . . . . . . . . . . . 63 ? 64 , 66 , 82 , 86 , 154 , 156 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mrq (memory read queues). . . . . . . . . . . . . . . . . .xxiii , 2 , 53 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 ? 65 , 69 , 154 mrs (memory request scheduler) . . . . . . . . . . . . xxiii , 65 ? 66 msb (most significant bit) . . . . . . . . .xxiii , 46 , 48 , 50 ? 51 , 75 mtrr (memory type and range registers) . . . . . . . . xxiii , 75 multiple page status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 multiplexer (mux). . . . . . . . . . . . . . . . . . . . . . . . . . see mux mux (multiplexer) . . . . . . . . . . . . . . . . . . . . . xxiii , 57 ? 58 , 67 mwf (memory write fifo) . . . . . . . . . . . . . . . . . . xxiii , 2 , 84 mwi (memory write-and-invalidate) . . . . . . . . . . . .xxiii , 4 , 9 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 166 mwq (memory write queue) . . . xxiii , 2 , 53 , 63 ? 66 , 69 , 154 mws (memory write selector) . . . . . . . . . . . . . . . xxiii , 63 , 66 n nand tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 43 nmi (non-maskable interrupt) . . . . . . . . . . . . . . . . . . xxiii , 28 non-maskable interrupt (nmi). . . . . . . . . . . . . . . . . see nmi o od (open drain). . . . . . . . . . . . . . . . . . . . . . . see open drain open drain . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii , 7 , 13 , 28 , 58 operating ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 operation, functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ordering rules, agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 p pa (physical address) . . . . . . . . . . . . . . . . . . xxiv , 48 , 51 , 106 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 , 207 type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 page directory entry (pde). . . . . . . . . . . . . . . . . . . . . . . see pde directory table (pdt). . . . . . . . . . . . . . . . . . . . . . . see pdt hit (ph). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see ph table entry (pte). . . . . . . . . . . . . . . . . . . . . . . . . . see pte tables (pt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see pt translation structures. . . . . . . . . . . . . . . . . . . . . . . . . . . 101 page directory entry (pde). . . . . . . . . . . . . . . . . . . . see pde par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ? 136 , 167 , 171 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 error detected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 167 error response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 pbga (plastic ball grid array) . . . . . . . . . . xxiv , 1 , 7 , 13 , 207 pc-100 sdram dimms. . . . . . . . . . 1 , 3 , 8 , 14 , 63 , 71 , 76 ? 77 pci (peripheral component interconnect) . . . . . . . xxiv , 1 ? 2 , . . . . . . . . . . . . . . . .4 ? 5 , 7 ? 8 , 50 , 52 ? 53 , 63 , 155 , 158 header type (device 0). . . . . . . . . . . . . . . . . . . . . . . . . . 138 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 targets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
210 index 21910d ? august 1999 preliminary information pci bus accesses by another initiator . . . . . . . . . . . . . . . . . . . . . . 86 ad[31:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 , 96 bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 configuration address . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 configuration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . . 127 configuration space enable . . . . . . . . . . . . . . . . . . . . . . 128 controller . . . . . . . . . . . . . . . . . . . xxvi , 4 , 9 ? 11 , 13 ? 14 , 82 device 0 registers (cpu-pci bridge). . . . . . . . . . . . . . . 134 device 1 registers (agp). . . . . . . . . . . . . . . . . . . . . . . . . 165 device number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 devsel#. . . . . . . . . . . . . . . . . . . . . . 24 , 135 ? 136 , 167 , 171 frame# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ? 23 , 25 function number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 gnt[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 irdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 memory-mapped control registers . . . . . . . . . . . . . . . . 177 number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 pci-from-memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 pci-to-memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 preq# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 primary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 secondary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 serr# . . . . . . . . . . . . . . . . . . . 134 ? 135 , 165 , 167 , 176 , 179 sideband signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 transactions on the agp bus. . . . . . . . . . . . . . . . . . . . . . . 97 trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 25 pci interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ad[31:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 c/be[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 devsel#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 frame# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 gnt[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 irdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 lock# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 preq# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 req[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 wsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pci/apci write queue (awq). . . . . . . . . . . . . . . . . see awq pci-pci capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 82 pde (page directory entry) . . . . . . . . . . . . xxiv , 101 ? 103 , 106 pdt (page directory table) . . . . . . . . . . . . . . . . xxiv , 102 , 106 pending probes queue (ppq). . . . . . . . . . . . . . . . . . .see ppq peripheral component interconnect (pci). . . . . . . . see pci pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 ? 27 , 84 ph (page hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv , 65 , 147 phase locked loop (pll). . . . . . . . . . . . . . . . . . . . . . see pll physical address (pa). . . . . . . . . . . . . . . . . . . . . . . . . . see pa physical page address (ppa). . . . . . . . . . . . . . . . . . . see ppa pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 functional groupings . . . . . . . . . . . . . . . . . . . . . . . 203 ? 204 names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 ? 204 numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 ? 204 pipe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 , 34 ? 35 , 40 , 96 pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 pipelined requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 plastic ball grid array (pbga). . . . . . . . . . . . . . . . see pbga pll (phase locked loop) . . . . . . . . . . . . . . . . . . . .xxiv , 14 , 114 pmsm (power management state machine) . . . . . . . xxiv , 112 pos (power-on suspend) . . . . . . . . . . . . . . . . . . . . . . . . xxiv , 13 post (power-on self-test) . . . . . . . . . . . . . . . . . . . . . . xxiv , 127 power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 110 , 181 acpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 power management state machine (pmsm). . . . see pmsm power-on self-test (post). . . . . . . . . . . . . . . . . . . . see post power-on suspend (pos). . . . . . . . . . . . . . . . . . . . . . see pos ppa (physical page address). . . . . . . . . . . . . . . .xxiv , 101 , 109 ppq (pending probes queue) . . . . . . . . . . . . . . . . . . . . xxiv , 53 pq (probe queue). . . . . . . . . . . . . . . . . . . . . . . . .xxiv , 2 , 53 ? 54 pra (probe response alert agent) . . . . . . . . . . . . . xxiv , 53 ? 54 prefetch buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 prefetchable graphics memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 memory-mapped control registers . . . . . . . . . . . . . . . . 140 preq#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ? 27 , 84 primary pci bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 probe queue (pq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . see pq probe response alert agent (pra). . . . . . . . . . . . . see pra probe system data and control queue (psq). . . . . see psq processor bus read from pci target . . . . . . . . . . . . . . . . . . . . . . . . . . 85 write to pci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 , 53 interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clkfwdrst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 procrdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 saddin[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddinclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddout[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddoutclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 scheck[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sdata[63:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 sdatainclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 sdatainval# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sdataoutclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . 21 sysclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 write posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 procrdy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 55 programming interface . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 psq (probe system data and control queue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv , 53 ? 54 pt (page tables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv , 102 pte (page table entries) . . . . . . . . . . . . . . .xxiv , 101 ? 102 , 109
index 211 21910d ? august 1999 preliminary information r ram (random access memory) . . . . . . . . . . . . . . . . . . . . . xxiv random access memory (ram). . . . . . . . . . . . . . . . see ram ras[5:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 , 76 rbf#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 rbn (round robin) . . . . . . . . . . . . . . . . . . . . . . . . . xxiv , 64 ? 65 rdq (read request queue). . . . . . . . . . . . . . . . . . . xxiv , 89 , 91 read acknowledge queue (rxa). . . . . . . . . . . . . . . . . . see rxa buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 only memory (rom). . . . . . . . . . . . . . . . . . . . . . . see rom request queue (rdq) . . . . . . . . . . . . . . . . . . . . xxiv , 89 , 91 read acknowledge queue (rxa). . . . . . . . . . . . . . . see rxa read/write request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 received target abort . . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xix , xxvi refresh state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi req[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 request queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ? 92 reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 revision agp specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 revision code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 memory-mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 rom (read only memory). . . . . . . . . . . . . . . . . . . . . . . . . . xxiv rom_sck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 60 rom_sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 round robin (rbn). . . . . . . . . . . . . . . . . . . . . . . . . . see rbn rxa (read acknowledge queue) . . . . . . . . . . . . . . . . . xxiv , 91 s saddin[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddinclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddout[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 saddoutclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sba (sideband address) . . . . . . . . . . . . . . . . . xxiv , 88 ? 90 , 161 bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 sba[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ? 35 , 41 ? 42 sbstb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 scan_en#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 scas# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 scas[2:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 scheck[7:0]#] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 sdata[63:0]#]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 sdatainclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 sdatainval# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sdataoutclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sdi (system dram interface) . . . xxiv , 12 , 82 , 86 , 89 , 91 , 94 sdram (synchronous dram) xxiv , 1 , 3 , 6 , 8 ? 9 , 13 ? 14 , 30 , 67 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 76 100-mhz scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 dimm loading analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 interface memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 memory organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 sdram memory controller (smc) . . . . . . . . . . . . xxiv , 68 secondary apci (agp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 10 , 52 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 serial initialization packet (sip). . . . . . . . . . . . . . . . . . . . . see sip presence detect (spd). . . . . . . . . . . . . . . . . . . . . . see spd read only memory (srom). . . . . . . . . . . . . . . . see srom serr# . . . . . . . . . . . . . . . . . . 28 , 134 ? 135 , 165 , 167 , 176 , 179 enable agp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 primary pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 secondary pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 settings, typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 shadow ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 sideband address (sba). . . . . . . . . . . . . . . . . . . . . . . see sba sideband signals pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 signaled initiator abort . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 system error . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 167 , 171 target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 , 167 , 171 signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . xix , 17 ? 43 , 201 ? 204 a_ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 34 , 40 ? 41 a_c/be#[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 35 , 41 a_clk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 , 35 a_devsel# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 a_frame#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 35 ? 37 , 97 a_gnt#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 , 42 a_irdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 37 a_par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 a_req# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 38 a_serr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_stop#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 a_trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 , 38 ad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 24 , 28 , 52 adstb0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c/be[3:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ? 24 cas[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 clkfwdrst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 58 connect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 , 57 cs[5:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 , 69 , 76 devsel# . . . . . . . . . . . . . . . . . . 23 ? 24 , 135 ? 136 , 167 , 171 dqm[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 , 76 frame# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ? 25 gnt[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 , 27 irdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 25 , 29 lock#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ma[13:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 mada[14:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 madb[14:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mcke[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 , 33 mdat[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 meccd[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 par . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
212 index 21910d ? august 1999 preliminary information pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 , 82 pgnt# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ? 27 pipe# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 , 34 ? 35 , 40 , 96 preq# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ? 27 procrdy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 rbf#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 req[4:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 rom_sck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 , 60 rom_sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 saddin[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 57 saddout[14:2]# . . . . . . . . . . . . . . . . . . . . . . . . . .18 , 58 ? 59 saddoutclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 58 sba[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ? 35 , 41 ? 42 sbstb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 scan_en#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 scas[2:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 scheck[7:0]#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 , 58 sdata[63:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 , 58 ? 59 sdatainclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 sdatainval# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 sdataoutclk[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . 21 , 59 serr# . . . . . . . . . . . . . . . .28 , 134 ? 135 , 165 , 167 , 176 , 179 sras# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 sras[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 st[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 42 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 136 , 167 , 171 sysclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 , 57 ? 58 trdy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 25 , 28 ? 29 tristate# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 we[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 , 76 wsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 sip (serial initialization packet) . . . . . . . . . . . . . .xxiv , 55 ? 57 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 ? 61 , 153 size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 smbus (system management bus). . . . . . . . . . . . . . . . . . . xxiv smc (sdram memory controller) . . . . . . . . . . . . xxiv , 67 ? 69 snoops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 53 source-synchronized clocking . . . . . . . . . . . . . . . . . . . . . . . . 7 spd (serial presence detect) . . . . . . . . . . . . . . . . . . . . xxiv , 71 special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 166 specifications package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 , 207 split transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 sram (synchronous ram) . . . . . . . . . . . . . . . . . . . . . xxiv , 76 sras# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 , 76 sras[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 srom (serial read only memory) . . . . . . . . . . . . . xxiv , 43 , 60 srq (sysdc read queue) . . . . . . . . . . . . . . . . . . . . . . . xxiv , 53 st[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 , 42 stop grant . . . . . . . . . . . . . . . . . . . . . . 5 , 13 , 49 , 111 ? 112 , 152 stop# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 , 136 , 167 , 171 stpclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 , 110 ? 112 subclass code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 , 168 switching characteristics . . . . . . . . . . . . . . . . . . . . . . 189 ? 191 synchronous direct random access memory (sdram). . . . . . . . . . . . . . . . . . see sdram synchronous dram (sdram). . . . . . . . . . . . . . see sdram synchronous random access memory (sram). . . . . . . . . . . . . . . . . . . . . . see sram sysaddout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 51 command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 sysclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 , 21 , 56 ? 57 , 73 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . 190 sysdc (system data commands). . . . . . . . xxiv , 53 , 58 , 61 ? 62 sysdc read queue (srq). . . . . . . . . . . . . . . . . . . . . see srq system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 data and control queue (csq). . . . . . . . . . . . . . . see csq data commands (sysdc). . . . . . . . . . . . . . . . . . see sysdc dram interface (sdi). . . . . . . . . . . . . . . . . . . . . . . see sdi interface. . . . . . . . . . . . . . . . . see amd athlon system bus management bus (smbus). . . . . . . . . . . . . . . . . see smbus t thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 tlb (translation lookaside buffer) . . . . . . . . xxiv , 89 , 91 , 99 , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ? 104 , 109 , 179 tom (top of memory) . . . . . . . . . . . . . . . . . . . . . . .xxiv , 47 , 52 top of memory (tom). . . . . . . . . . . . . . . . . . . . . . . . .see tom transaction combiner agent (xca). . . . . . . . . . . . . see xca transaction queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 transfer rate capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 transistor transistor logic (ttl). . . . . . . . . . . . . . . see ttl translation lookaside buffer (tlb). . . . . . . . . . . . . see tlb trdy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 , 25 , 28 ? 29 tristate#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ttl (transistor transistor logic) . . . . . . . . . . . . . . . . . . . . . xxiv typical settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 u universal serial bus (usb). . . . . . . . . . . . . . . . . . . . . see usb usb (universal serial bus). . . . . . . . . . . . . . . . . . . . . . . . xxv , 6 user-defined features. . . . . . . . . . . . . . . . . . . . . 136 , 167 , 172 v valid bit error capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 valid delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 vas (virtual address space) . . . . . . . . . . . . . . . . . . . . xxv , 163 vga enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 isa address space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 palette snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 , 166 vga (video graphics adapter) . . xxv , 47 , 135 , 155 , 158 , 162 video graphics adapter (vga). . . . . . . . . . . . . . . . . see vga virtual address space (vas). . . . . . . . . . . . . . . . . . . see vas virtual page address (vpa). . . . . . . . . . . . . . . . . . . . see vpa voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 , 199 vpa (virtual page address) . . . . . . . . . . . . . . . . . . . . . xxv , 105
index 213 21910d ? august 1999 preliminary information w wbt (write buffer tag) . . . . . . . . . . . . . . . . . . . .xxv , 89 , 91 ? 92 we[2:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 , 76 website (www.amd.com) . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi whami (who am i). . . . . . . . . . . . . . . . . . . xxv , 131 , 155 , 181 who am i (whami). . . . . . . . . . . . . . . . . . . . . . . see whami wp (write protect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv write buffer tag (wbt) . . . . . . . . . . . . . . . . . . . . . . . . . xxv , 91 ? 92 buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ? 62 , 82 , 85 posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 request queue (wrq). . . . . . . . . . . . . . . . . . . . . xxv , 89 , 91 writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 , 135 wrq (write request queue). . . . . . . . . . . . . . . . . . . xxv , 89 , 91 wsc# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 x x86 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvi xca (transaction combiner agent) . . . . . . . . . . . . . xxv , 53 ? 54 z zdb (zero delay buffer) . . . . . . . . . . . . . . . xxv , 33 , 77 , 79 , 81 zero delay buffer (zdb). . . . . . . . . . . . . . . . . . . . . . .see zdb
214 index 21910d ? august 1999 preliminary information

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